The vinsgr2vr/vpickve2gr instructions need use get_src/get_dst to get
gpr registers value, not cpu_gpr[]. The $zero register does not
have cpu_gpr[0] allocated.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/insn_trans/trans_lsx.c.inc | 36 ++++++++++++++-------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 0be2b5a3a8..312ce0475f 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -3963,96 +3963,108 @@ TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)
static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st8_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
return true;
}
static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st16_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
return true;
}
static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st32_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
return true;
}
static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
{
+ TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
- tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env,
+ tcg_gen_st_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
return true;
}
static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld8s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}
static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld16s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}
static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld32s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}
static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}
static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld8u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}
static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld16u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}
static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld32u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}
static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
{
+ TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
- tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
+ tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}
--
2.39.1
