[PULL 1/2] target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADV

[Song Gao]

1.helper_asrtle_d/helper_asrtgt_d need use GETPC() to get PC;
2 LD/ST{LE/GT} need set CSR_BADV = gpr[rj];
3 ASRTLE.D/ASRTGT.D also write CSR_BADV, but this value is random
  and has no reference value.

Signed-off-by: Song Gao <gaos...@loongson.cn>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20230515130042.2719712-1-gaos...@loongson.cn>
---
 target/loongarch/cpu.c       | 2 +-
 target/loongarch/op_helper.c | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c0afc21b2f..ad93ecac92 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -187,10 +187,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
     case EXCCODE_IPE:
     case EXCCODE_FPD:
     case EXCCODE_FPE:
-    case EXCCODE_BCE:
     case EXCCODE_SXD:
         env->CSR_BADV = env->pc;
         QEMU_FALLTHROUGH;
+    case EXCCODE_BCE:
     case EXCCODE_ADEM:
     case EXCCODE_PIL:
     case EXCCODE_PIS:
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 568c071601..60335a05e2 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -49,14 +49,16 @@ target_ulong helper_bitswap(target_ulong v)
 void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
 {
     if (rj > rk) {
-        do_raise_exception(env, EXCCODE_BCE, 0);
+        env->CSR_BADV = rj;
+        do_raise_exception(env, EXCCODE_BCE, GETPC());
     }
 }
 
 void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
 {
     if (rj <= rk) {
-        do_raise_exception(env, EXCCODE_BCE, 0);
+        env->CSR_BADV = rj;
+        do_raise_exception(env, EXCCODE_BCE, GETPC());
     }
 }
 
-- 
2.39.1