A set of small fixes for the interrupt controller (xive2) on P10. Frederic Barrat (4): pnv/xive2: Add definition for TCTXT Config register pnv/xive2: Add definition for the ESB cache configuration register pnv/xive2: Allow writes to the Physical Thread Enable registers pnv/xive2: Handle TIMA access through all ports
hw/intc/pnv_xive2.c | 20 +++++++++++++++++++- hw/intc/pnv_xive2_regs.h | 8 ++++++++ hw/intc/xive.c | 18 ++++++++++++++++++ 3 files changed, 45 insertions(+), 1 deletion(-) -- 2.40.1
