If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
Linux Kernel will fail to detect the availability of the CBOM/CBOZ
extensions, regardless of the contents of the 'riscv,isa' DT prop.
The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes,
so let's use them. We'll also expose them as user flags like it is
already done with TCG.
However, in contrast with what happens with TCG, the user is not able to
set any value that is different from the 'host' value. And KVM can be
harsh dealing with it: a ENOTSUPP can be thrown for the mere attempt of
executing kvm_set_one_reg() for these 2 regs.
We'll read the 'host' value and use it to set these values, regardless of
user choice. If the user happened to chose a different value, error out.
We'll also error out if we failed to read the block sizes.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
---
target/riscv/kvm.c | 94 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 92 insertions(+), 2 deletions(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 92b99fe261..7789d835e5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -241,8 +241,16 @@ static void kvm_cpu_cfg_set(RISCVCPU *cpu,
RISCVCPUMultiExtConfig *multi_ext,
uint32_t val)
{
int cpu_cfg_offset = multi_ext->cpu_cfg_offset;
- bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
+ uint16_t *blocksize;
+ bool *ext_enabled;
+ if (strstr(multi_ext->name, "blocksize")) {
+ blocksize = (void *)&cpu->cfg + cpu_cfg_offset;
+ *blocksize = val;
+ return;
+ }
+
+ ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
*ext_enabled = val;
}
@@ -250,8 +258,15 @@ static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu,
RISCVCPUMultiExtConfig *multi_ext)
{
int cpu_cfg_offset = multi_ext->cpu_cfg_offset;
- bool *ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
+ uint16_t *blocksize;
+ bool *ext_enabled;
+ if (strstr(multi_ext->name, "blocksize")) {
+ blocksize = (void *)&cpu->cfg + cpu_cfg_offset;
+ return *blocksize;
+ }
+
+ ext_enabled = (void *)&cpu->cfg + cpu_cfg_offset;
return *ext_enabled;
}
@@ -295,6 +310,33 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor
*v,
kvm_cpu_cfg_set(cpu, multi_ext_cfg, value);
}
+/*
+ * We'll avoid extra complexity by always assuming this
+ * array order with cbom first.
+ */
+static RISCVCPUMultiExtConfig kvm_cbomz_blksize_cfgs[] = {
+ {.name = "cbom_blocksize", .cpu_cfg_offset = CPUCFG(cbom_blocksize),
+ .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)},
+ {.name = "cboz_blocksize", .cpu_cfg_offset = CPUCFG(cboz_blocksize),
+ .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)},
+};
+
+static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v,
+ const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPUMultiExtConfig *cbomz_size_cfg = opaque;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ uint16_t value;
+
+ if (!visit_type_uint16(v, name, &value, errp)) {
+ return;
+ }
+
+ cbomz_size_cfg->user_set = true;
+ kvm_cpu_cfg_set(cpu, cbomz_size_cfg, value);
+}
+
static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
{
CPURISCVState *env = &cpu->env;
@@ -321,6 +363,45 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU
*cpu, CPUState *cs)
}
}
+static void kvm_riscv_finalize_features(RISCVCPU *cpu, CPUState *cs)
+{
+ CPURISCVState *env = &cpu->env;
+ uint64_t id, reg;
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(kvm_cbomz_blksize_cfgs); i++) {
+ RISCVCPUMultiExtConfig *cbomz_cfg = &kvm_cbomz_blksize_cfgs[i];
+ uint64_t host_val;
+
+ if ((i == 0 && !cpu->cfg.ext_icbom) ||
+ (i == 1 && !cpu->cfg.ext_icboz)) {
+ continue;
+ }
+
+ id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+ cbomz_cfg->kvm_reg_id);
+
+ ret = kvm_get_one_reg(cs, id, &host_val);
+ if (ret != 0) {
+ error_report("Unable to read KVM reg val %s, error %d",
+ cbomz_cfg->name, ret);
+ exit(EXIT_FAILURE);
+ }
+
+ if (cbomz_cfg->user_set) {
+ reg = kvm_cpu_cfg_get(cpu, cbomz_cfg);
+ if (reg != host_val) {
+ error_report("Unable to set %s to a different value than "
+ "the host (%lu)",
+ cbomz_cfg->name, host_val);
+ exit(EXIT_FAILURE);
+ }
+ }
+
+ kvm_cpu_cfg_set(cpu, cbomz_cfg, host_val);
+ }
+}
+
static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
{
int i;
@@ -344,6 +425,14 @@ static void kvm_riscv_add_cpu_user_properties(Object
*cpu_obj)
kvm_cpu_set_multi_ext_cfg,
NULL, multi_cfg);
}
+
+ for (i = 0; i < ARRAY_SIZE(kvm_cbomz_blksize_cfgs); i++) {
+ RISCVCPUMultiExtConfig *cbomz_size_cfg = &kvm_cbomz_blksize_cfgs[i];
+
+ object_property_add(cpu_obj, cbomz_size_cfg->name, "uint16",
+ NULL, kvm_cpu_set_cbomz_blksize,
+ NULL, cbomz_size_cfg);
+ }
}
void kvm_riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
@@ -856,6 +945,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
kvm_riscv_update_cpu_misa_ext(cpu, cs);
kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
+ kvm_riscv_finalize_features(cpu, cs);
return ret;
}
--
2.40.1
