The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang <wangyuquan1...@phytium.com.cn>
Change-Id: I1376f8bbc0e25dcd9d8a22b6e061cb56b3486394
---
hw/arm/sbsa-ref.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index de21200ff9..4c9a942a63 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -82,7 +82,7 @@ enum {
SBSA_SECURE_UART_MM,
SBSA_SECURE_MEM,
SBSA_AHCI,
- SBSA_EHCI,
+ SBSA_XHCI,
};
struct SBSAMachineState {
@@ -119,7 +119,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_SMMU] = { 0x60050000, 0x00020000 },
/* Space here reserved for more SMMUs */
[SBSA_AHCI] = { 0x60100000, 0x00010000 },
- [SBSA_EHCI] = { 0x60110000, 0x00010000 },
+ [SBSA_XHCI] = { 0x60110000, 0x00010000 },
/* Space here reserved for other devices */
[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
/* 32-bit address PCIE MMIO space */
@@ -139,7 +139,7 @@ static const int sbsa_ref_irqmap[] = {
[SBSA_SECURE_UART] = 8,
[SBSA_SECURE_UART_MM] = 9,
[SBSA_AHCI] = 10,
- [SBSA_EHCI] = 11,
+ [SBSA_XHCI] = 11,
[SBSA_SMMU] = 12, /* ... to 15 */
[SBSA_GWDT_WS0] = 16,
};
@@ -575,12 +575,12 @@ static void create_ahci(const SBSAMachineState *sms)
}
}
-static void create_ehci(const SBSAMachineState *sms)
+static void create_xhci(const SBSAMachineState *sms)
{
- hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
- int irq = sbsa_ref_irqmap[SBSA_EHCI];
+ hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
+ int irq = sbsa_ref_irqmap[SBSA_XHCI];
- sysbus_create_simple("platform-ehci-usb", base,
+ sysbus_create_simple("sysbus-xhci", base,
qdev_get_gpio_in(sms->gic, irq));
}
@@ -803,7 +803,7 @@ static void sbsa_ref_init(MachineState *machine)
create_ahci(sms);
- create_ehci(sms);
+ create_xhci(sms);
create_pcie(sms);
--
2.34.1
