On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote: > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ============================================================= > * mnscratch (0x740) > * mnepc (0x741) > * mncause (0x742) > * mnstatus (0x744) > ============================================================= > * mnret: To return from RNMI interrupt/exception handler. > ============================================================= > > RNMI also has higher priority than any other interrupts or exceptions > and cannot be disabled by software. > > RNMI may be used to route to other devices such as Bus Error Unit or > Watchdog Timer in the future. > > The interrupt/exception trap handler addresses of RNMI are > implementation defined.
Is there an M-mode software PoC for this with implemented handlers? Thanks, drew > > Changelog: > > v4 > * Fix some coding style issues. > ( Thank Daniel for the suggestions. ) > > v3 > * Update to the newest version of Smrnmi extension specification. > > v2 > * split up the series into more commits for convenience of review. > * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. > > Tommy Wu (4): > target/riscv: Add Smrnmi cpu extension. > target/riscv: Add Smrnmi CSRs. > target/riscv: Handle Smrnmi interrupt and exception. > target/riscv: Add Smrnmi mnret instruction. > > hw/riscv/riscv_hart.c | 21 +++++ > include/hw/riscv/riscv_hart.h | 4 + > target/riscv/cpu.c | 18 ++++ > target/riscv/cpu.h | 11 +++ > target/riscv/cpu_bits.h | 23 ++++++ > target/riscv/cpu_helper.c | 81 ++++++++++++++++-- > target/riscv/csr.c | 82 +++++++++++++++++++ > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 + > .../riscv/insn_trans/trans_privileged.c.inc | 12 +++ > target/riscv/op_helper.c | 49 +++++++++++ > 11 files changed, 300 insertions(+), 5 deletions(-) > > -- > 2.31.1 > >
