This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 36 ++++++++++++++++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 36 ++++++++++++++++++++
target/loongarch/insns.decode | 33 ++++++++++++++++++
3 files changed, 105 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 2f1da9db80..0c1c7a7e6e 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2040,6 +2040,42 @@ INSN_LASX(xvori_b, xx_i)
INSN_LASX(xvxori_b, xx_i)
INSN_LASX(xvnori_b, xx_i)
+INSN_LASX(xvsll_b, xxx)
+INSN_LASX(xvsll_h, xxx)
+INSN_LASX(xvsll_w, xxx)
+INSN_LASX(xvsll_d, xxx)
+INSN_LASX(xvslli_b, xx_i)
+INSN_LASX(xvslli_h, xx_i)
+INSN_LASX(xvslli_w, xx_i)
+INSN_LASX(xvslli_d, xx_i)
+
+INSN_LASX(xvsrl_b, xxx)
+INSN_LASX(xvsrl_h, xxx)
+INSN_LASX(xvsrl_w, xxx)
+INSN_LASX(xvsrl_d, xxx)
+INSN_LASX(xvsrli_b, xx_i)
+INSN_LASX(xvsrli_h, xx_i)
+INSN_LASX(xvsrli_w, xx_i)
+INSN_LASX(xvsrli_d, xx_i)
+
+INSN_LASX(xvsra_b, xxx)
+INSN_LASX(xvsra_h, xxx)
+INSN_LASX(xvsra_w, xxx)
+INSN_LASX(xvsra_d, xxx)
+INSN_LASX(xvsrai_b, xx_i)
+INSN_LASX(xvsrai_h, xx_i)
+INSN_LASX(xvsrai_w, xx_i)
+INSN_LASX(xvsrai_d, xx_i)
+
+INSN_LASX(xvrotr_b, xxx)
+INSN_LASX(xvrotr_h, xxx)
+INSN_LASX(xvrotr_w, xxx)
+INSN_LASX(xvrotr_d, xxx)
+INSN_LASX(xvrotri_b, xx_i)
+INSN_LASX(xvrotri_h, xx_i)
+INSN_LASX(xvrotri_w, xx_i)
+INSN_LASX(xvrotri_d, xx_i)
+
INSN_LASX(xvreplgr2vr_b, xr)
INSN_LASX(xvreplgr2vr_h, xr)
INSN_LASX(xvreplgr2vr_w, xr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index d48f76f118..5d7deb312e 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -1977,6 +1977,42 @@ static void do_xvnori_b(unsigned vece, uint32_t xd_ofs,
uint32_t xj_ofs,
TRANS(xvnori_b, gvec_xx_i, MO_8, do_xvnori_b)
+TRANS(xvsll_b, gvec_xxx, MO_8, tcg_gen_gvec_shlv)
+TRANS(xvsll_h, gvec_xxx, MO_16, tcg_gen_gvec_shlv)
+TRANS(xvsll_w, gvec_xxx, MO_32, tcg_gen_gvec_shlv)
+TRANS(xvsll_d, gvec_xxx, MO_64, tcg_gen_gvec_shlv)
+TRANS(xvslli_b, gvec_xx_i, MO_8, tcg_gen_gvec_shli)
+TRANS(xvslli_h, gvec_xx_i, MO_16, tcg_gen_gvec_shli)
+TRANS(xvslli_w, gvec_xx_i, MO_32, tcg_gen_gvec_shli)
+TRANS(xvslli_d, gvec_xx_i, MO_64, tcg_gen_gvec_shli)
+
+TRANS(xvsrl_b, gvec_xxx, MO_8, tcg_gen_gvec_shrv)
+TRANS(xvsrl_h, gvec_xxx, MO_16, tcg_gen_gvec_shrv)
+TRANS(xvsrl_w, gvec_xxx, MO_32, tcg_gen_gvec_shrv)
+TRANS(xvsrl_d, gvec_xxx, MO_64, tcg_gen_gvec_shrv)
+TRANS(xvsrli_b, gvec_xx_i, MO_8, tcg_gen_gvec_shri)
+TRANS(xvsrli_h, gvec_xx_i, MO_16, tcg_gen_gvec_shri)
+TRANS(xvsrli_w, gvec_xx_i, MO_32, tcg_gen_gvec_shri)
+TRANS(xvsrli_d, gvec_xx_i, MO_64, tcg_gen_gvec_shri)
+
+TRANS(xvsra_b, gvec_xxx, MO_8, tcg_gen_gvec_sarv)
+TRANS(xvsra_h, gvec_xxx, MO_16, tcg_gen_gvec_sarv)
+TRANS(xvsra_w, gvec_xxx, MO_32, tcg_gen_gvec_sarv)
+TRANS(xvsra_d, gvec_xxx, MO_64, tcg_gen_gvec_sarv)
+TRANS(xvsrai_b, gvec_xx_i, MO_8, tcg_gen_gvec_sari)
+TRANS(xvsrai_h, gvec_xx_i, MO_16, tcg_gen_gvec_sari)
+TRANS(xvsrai_w, gvec_xx_i, MO_32, tcg_gen_gvec_sari)
+TRANS(xvsrai_d, gvec_xx_i, MO_64, tcg_gen_gvec_sari)
+
+TRANS(xvrotr_b, gvec_xxx, MO_8, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_h, gvec_xxx, MO_16, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_w, gvec_xxx, MO_32, tcg_gen_gvec_rotrv)
+TRANS(xvrotr_d, gvec_xxx, MO_64, tcg_gen_gvec_rotrv)
+TRANS(xvrotri_b, gvec_xx_i, MO_8, tcg_gen_gvec_rotri)
+TRANS(xvrotri_h, gvec_xx_i, MO_16, tcg_gen_gvec_rotri)
+TRANS(xvrotri_w, gvec_xx_i, MO_32, tcg_gen_gvec_rotri)
+TRANS(xvrotri_d, gvec_xx_i, MO_64, tcg_gen_gvec_rotri)
+
static bool gvec_dupx(DisasContext *ctx, arg_xr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ce2ad47b88..03c3aa0019 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1641,6 +1641,39 @@ xvori_b 0111 01111101 01 ........ ..... .....
@xx_ui8
xvxori_b 0111 01111101 10 ........ ..... ..... @xx_ui8
xvnori_b 0111 01111101 11 ........ ..... ..... @xx_ui8
+xvsll_b 0111 01001110 10000 ..... ..... ..... @xxx
+xvsll_h 0111 01001110 10001 ..... ..... ..... @xxx
+xvsll_w 0111 01001110 10010 ..... ..... ..... @xxx
+xvsll_d 0111 01001110 10011 ..... ..... ..... @xxx
+xvslli_b 0111 01110010 11000 01 ... ..... ..... @xx_ui3
+xvslli_h 0111 01110010 11000 1 .... ..... ..... @xx_ui4
+xvslli_w 0111 01110010 11001 ..... ..... ..... @xx_ui5
+xvslli_d 0111 01110010 1101 ...... ..... ..... @xx_ui6
+xvsrl_b 0111 01001110 10100 ..... ..... ..... @xxx
+xvsrl_h 0111 01001110 10101 ..... ..... ..... @xxx
+xvsrl_w 0111 01001110 10110 ..... ..... ..... @xxx
+xvsrl_d 0111 01001110 10111 ..... ..... ..... @xxx
+xvsrli_b 0111 01110011 00000 01 ... ..... ..... @xx_ui3
+xvsrli_h 0111 01110011 00000 1 .... ..... ..... @xx_ui4
+xvsrli_w 0111 01110011 00001 ..... ..... ..... @xx_ui5
+xvsrli_d 0111 01110011 0001 ...... ..... ..... @xx_ui6
+xvsra_b 0111 01001110 11000 ..... ..... ..... @xxx
+xvsra_h 0111 01001110 11001 ..... ..... ..... @xxx
+xvsra_w 0111 01001110 11010 ..... ..... ..... @xxx
+xvsra_d 0111 01001110 11011 ..... ..... ..... @xxx
+xvsrai_b 0111 01110011 01000 01 ... ..... ..... @xx_ui3
+xvsrai_h 0111 01110011 01000 1 .... ..... ..... @xx_ui4
+xvsrai_w 0111 01110011 01001 ..... ..... ..... @xx_ui5
+xvsrai_d 0111 01110011 0101 ...... ..... ..... @xx_ui6
+xvrotr_b 0111 01001110 11100 ..... ..... ..... @xxx
+xvrotr_h 0111 01001110 11101 ..... ..... ..... @xxx
+xvrotr_w 0111 01001110 11110 ..... ..... ..... @xxx
+xvrotr_d 0111 01001110 11111 ..... ..... ..... @xxx
+xvrotri_b 0111 01101010 00000 01 ... ..... ..... @xx_ui3
+xvrotri_h 0111 01101010 00000 1 .... ..... ..... @xx_ui4
+xvrotri_w 0111 01101010 00001 ..... ..... ..... @xx_ui5
+xvrotri_d 0111 01101010 0001 ...... ..... ..... @xx_ui6
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @xr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @xr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @xr
--
2.39.1
