Hi, Richard
在 2023/6/20 下午8:09, Richard Henderson 写道:
On 6/20/23 11:37, Song Gao wrote:
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index b23f38c3d5..347950b4d0 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -259,9 +259,23 @@ typedef union VReg {
Int128 Q[LSX_LEN / 128];
}VReg;
+#define LASX_LEN (256)
+typedef union XReg {
+ int8_t XB[LASX_LEN / 8];
+ int16_t XH[LASX_LEN / 16];
+ int32_t XW[LASX_LEN / 32];
+ int64_t XD[LASX_LEN / 64];
+ uint8_t UXB[LASX_LEN / 8];
+ uint16_t UXH[LASX_LEN / 16];
+ uint32_t UXW[LASX_LEN / 32];
+ uint64_t UXD[LASX_LEN / 64];
+ Int128 XQ[LASX_LEN / 128];
+} XReg;
This is following the example of target/i386, and I think it is a bad
example.
[....]
For Arm, we have one ARMVectorReg which covers AdvSIMD (128-bit) and
SVE (2048-bit).
I would prefer if you just expand the definition of VReg to be 256 bits.
Ok, I will correct it on v2.
Thanks.
Song Gao
