On Thu, Feb 16, 2012 at 12:17:02PM +1000, Peter A. G. Crosthwaite wrote: > This is a suite of Device models and a machine model for the Xilinx Zynq-7000 > Extensible Processing Platform: > > http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm > > This is an ARM based platform featuring embedded SoC peripherals. This patch > series includes a minimal set of device models and a a machine model capable > of emulating zynq platforms booting linux. > > This first 3 patches in this series are device models for IP provided by > cadence for the Zynq platform. The final patch is the initial revision of the > zynq machine model. > > Most of this work was originally authored by Xilinx, as indicated by (c) > notices in added files. > > Tree is available from: > git://developer.petalogix.com/private/peterc/qemu.git > branch: zynq-initial.5 > > --- > changed from v4: > fixed FSF addess (1/4) (2/4) (4/4) > changed device_init -> type_init (all) > changed from v3: > fixed timer race condition issue (2/4) > changed from v2: > fixed timer prescision issue (2/4) > fixed compile warnings in zynq_arm_sysctl (4/4) > changes from v1: > formatting and style fixes > updated for QOM > removed former patch 3 (cadence WDT device model) - not required > removed former patch 5 (dtb argument) - this is currently under discussion in > other patch series' > removed former patch 6 (initrd parameterisation) - not required for minimal > boot
Looks good Acked-by: Edgar E. Iglesias <edgar.igles...@gmail.com> Thanks, Edgar
