A last small test of bug fixes before rc1. thanks -- PMM
The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637: Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717 for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4: hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100) ---------------------------------------------------------------- target-arm queue: * hw/arm/sbsa-ref: set 'slots' property of xhci * linux-user: Remove pointless NULL check in clock_adjtime handling * ptw: Fix S1_ptw_translate() debug path * ptw: Account for FEAT_RME when applying {N}SW, SA bits * accel/tcg: Zero-pad PC in TCG CPU exec trace lines * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write ---------------------------------------------------------------- Peter Maydell (5): linux-user: Remove pointless NULL check in clock_adjtime handling target/arm/ptw.c: Add comments to S1Translate struct fields target/arm: Fix S1_ptw_translate() debug path target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits accel/tcg: Zero-pad PC in TCG CPU exec trace lines Tong Ho (1): hw/nvram: Avoid unnecessary Xilinx eFuse backstore write Yuquan Wang (1): hw/arm/sbsa-ref: set 'slots' property of xhci accel/tcg/cpu-exec.c | 4 +-- accel/tcg/translate-all.c | 2 +- hw/arm/sbsa-ref.c | 1 + hw/nvram/xlnx-efuse.c | 11 ++++-- linux-user/syscall.c | 12 +++---- target/arm/ptw.c | 90 +++++++++++++++++++++++++++++++++++++++++------ 6 files changed, 98 insertions(+), 22 deletions(-)
