The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1 for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179: target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000) ---------------------------------------------------------------- Fourth RISC-V PR for 8.1 * Fix LMUL check to use VLEN * Fix typo field in NUMA error_report * check priv_ver before auto-enable zca/zcd/zcf * Fix disas output of upper immediates * tidy CPU firmware section ---------------------------------------------------------------- Christoph Müllner (1): riscv/disas: Fix disas output of upper immediates Daniel Henrique Barboza (2): docs/system/target-riscv.rst: tidy CPU firmware section target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf Rob Bradford (1): target/riscv: Fix LMUL check to use VLEN Zhao Liu (1): hw/riscv: Fix typo field in error_report docs/system/target-riscv.rst | 24 ++++++++++++++++-------- disas/riscv.h | 2 ++ disas/riscv.c | 19 ++++++++++++++++--- hw/riscv/numa.c | 4 ++-- target/riscv/cpu.c | 3 ++- target/riscv/vector_helper.c | 4 ++-- 6 files changed, 40 insertions(+), 16 deletions(-)
