* Richard Henderson <richard.hender...@linaro.org>:
> On 8/5/23 09:47, Helge Deller wrote:
> > Do we want to enable such an performance optimization?
> > If so, I see two possibilities:
> >
> > a) Re-define NB_MMU_MODES per target
>
> No, we've just gotten rid of per target definitions of NB_MMU_MODES, on the
> way to being able to support multiple targets simultaneously.
Ok, I assume that answer :-)
> This only affects x86, and for only 6 bytes per memory access. While saving
> code size is a nice goal, I sincerely doubt you can measure any performance
> difference.
Maybe. I don't know. I'm sure the gain is small, but the patch is small
too.
> If there were a way to change no more than two lines of code, that would be
> fine. But otherwise I don't see this as being worth making the rest of the
> code base any more complex.
Ok. What about that 6-line patch below for x86?
It's trivial and all what's needed for x86.
Btw, any index which is >= 9 will use the shorter code sequence.
Helge
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e0771a1043..3e71e666db 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2251,11 +2251,11 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_list x86_cpu_list
/* MMU modes definitions */
-#define MMU_KSMAP_IDX 0
-#define MMU_USER_IDX 1
-#define MMU_KNOSMAP_IDX 2
-#define MMU_NESTED_IDX 3
-#define MMU_PHYS_IDX 4
+#define MMU_KSMAP_IDX 11
+#define MMU_USER_IDX 12
+#define MMU_KNOSMAP_IDX 13
+#define MMU_NESTED_IDX 14
+#define MMU_PHYS_IDX 15
static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
{
