On 8/23/23 07:59, Jonathan Cameron via wrote:
On Mon, 14 Aug 2023 11:13:58 +0100
Alex Bennée <alex.ben...@linaro.org> wrote:
Jonathan Cameron <jonathan.came...@huawei.com> writes:
Used to drive the MPAM cache intialization and to exercise more
of the PPTT cache entry generation code. Perhaps a default
L3 cache is acceptable for max?
Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
---
target/arm/tcg/cpu64.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 8019f00bc3..2af67739f6 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -711,6 +711,17 @@ void aarch64_max_tcg_initfn(Object *obj)
uint64_t t;
uint32_t u;
+ /*
+ * Expanded cache set
+ */
+ cpu->clidr = 0x8204923; /* 4 4 4 4 3 in 3 bit fields */
+ cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 unified cache */
+ cpu->ccsidr[4] = 0x000007ff0000007cull; /* 2MB L3 cache 128B line */
+ cpu->ccsidr[6] = 0x00007fff0000007cull; /* 16MB L4 cache 128B line */
+ cpu->ccsidr[8] = 0x0007ffff0000007cull; /* 2048MB L5 cache 128B line */
+
I think Peter in another thread wondered if we should have a generic
function for expanding the cache idr registers based on a abstract lane
definition.
Great!
This response?
https://lore.kernel.org/qemu-devel/cafeaca_lzj1leutmro72fcfqicwtopd+5b-ypcfkv8bg1f+...@mail.gmail.com/
Followed up with
https://lore.kernel.org/qemu-devel/20230811214031.171020-6-richard.hender...@linaro.org/
r~
