On Fri, 11 Aug 2023 at 22:41, Richard Henderson <richard.hender...@linaro.org> wrote: > > Support all of the easy GM block sizes. > Use direct memory operations, since the pointers are aligned. > > While BS=2 (16 bytes, 1 tag) is a legal setting, that requires > an atomic store of one nibble. This is not difficult, but there > is also no point in supporting it until required. > > Note that cortex-a710 sets GM blocksize to match its cacheline > size of 64 bytes. I expect many implementations will also > match the cacheline, which makes 16 bytes very unlikely. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > ---
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
