This part of the patchset connects the nest1 chiplet model to p10 chip. Signed-off-by: Chalapathi V <chalapath...@linux.ibm.com> --- hw/ppc/pnv.c | 11 +++++++++++ include/hw/ppc/pnv_chip.h | 2 ++ 2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index eb54f93986..0e1c944753 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1660,6 +1660,8 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); + object_initialize_child(obj, "nest1_chiplet", &chip10->nest1_chiplet, + TYPE_PNV_NEST1_CHIPLET); chip->num_pecs = pcc->num_pecs; @@ -1829,6 +1831,15 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), &chip10->homer.regs); + /* nest1 chiplet control regs */ + object_property_set_link(OBJECT(&chip10->nest1_chiplet), "chip", + OBJECT(chip), &error_abort); + if (!qdev_realize(DEVICE(&chip10->nest1_chiplet), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE, + &chip10->nest1_chiplet.xscom_ctrl_regs); + /* PHBs */ pnv_chip_power10_phb_realize(chip, &local_err); if (local_err) { diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 53e1d921d7..4bcb92595a 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,7 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_nest_chiplet.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -109,6 +110,7 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; + PnvNest1Chiplet nest1_chiplet; uint32_t nr_quads; PnvQuad *quads; -- 2.31.1