Am Samstag, den 12.03.2011, 07:20 +0000 schrieb Adrian Ives: > Dave, > > That's all very nice and would be an absolutely fantastic piece of hardware > but it's very complex and likely to be expensive. I would have thought > that a better use of the development cost and time would be an FPGA-based QL > clone running at 80MHZ with 1GB RAM and onboard USB3, SATA and HDMI. > > SPI otoh is a very simple protocol and the only hardware needed are four I/O > lines for Clock, In, Out and Slave Select. When I finally get some time I > will look at the spare I/O provided on the superHermes to see if that could > be used for this purpose. > > Adrian Adrian, Dave, while this might sound a bit naive, I doubt whether there would be much HW involved when trying to build a bit-bang interface to SPI. SPI is such dead simple that you could connect CLOCK to an address line, MISO to the data bus and MOSI to another address line (Suitable buffering and 5V/3.3V conversion would have to be provided, The ROMCS line needs to be married with the rest of the pins through some minimal logic). The rest would be a matter of clever software. The QL ROM port already is quite de-coupled from the Bus with complete address decoding so that this could actually work.
What I would really like would be a small board connecting to the ROM slot, carrying a small CPLD for the decoding, an AVR controller, probably an Ethernet chip and an SD socket, maybe minimal USB hardware to connect USB mouse and keyboard. Dave, I like your idea with an FGPA based QL very much as it has lots of opportunities in it, but I think it's well beyond the capabilities of the current (small) QL scene, both regarding to Hardware and Software support. Start small! There's time for the more ambitious projects later. Tobias _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
