All, Sorry to be using another system that may quickly join our other platforms as an irrelevant footnote of computing history, but ...
Pictures of the latest Q-BUS Prototype are now at our Facebook page: http://www.facebook.com/memory.lane.computing The latest Q-BUS version has been modified to use the expansion connector on the new QL ROM card and has some additional control port logic which improves the reliability of the interface with the PIC chip. I think it's obvious that a commercial product based upon a design using so much discrete logic is really a non-starter, so this has to be seen as a proof of concept which would be translated into a solution using a CPLD with the minimum of additional components. It's also highly likely that the final solution (if there is one) will use SPI rather than the parallel ports seen here ... and may look nothing like this :) On one of the pictures you will notice the rather unique practice of mounting two 14 pin DIPs upside-down on top of each other ;) This is because the three NAND gates from the old QL ROM cartridge card, which was originally used to make the connection to the QL, have been moved onto the Q-BUS board and there wasn't room for the 74HCT10 without a complete rebuild. The "daughter" board, perched precariously on top of the main board, contains the logic for the control port; most importantly the lines ~ATTN and ~BUSY which are used to handshake with the PIC. The 34 pin box header at the "front" of the board connects to the QL ROM Card, the 25 pin connector at the "back" brings out the Q-BUS interface. The two connectors on the daughter board expose the control port and auxiliary address decode lines. All of this logic maps the Read Data port to $FE00, Read Control Register to $FE01, Select Device to $FDxx, Write Control to $FCxx and Write Data to $FFxx (where xx represents a data or control byte in the low order eight bits of the address) Even if this design doesn't make it through to production in its present form, this has definitely been a useful project to test the capabilities and reliability of the ROM port. Adrian www.memorylanecomputing.com _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
