I did a fair bit of work on QL2 before hitting the wall in 2014. I recently
went back over my documentation. While I still think the idea has merit, I
don't know if it is something I can work on. For that reason, I thought I'd
share some of the design decisions I'd made, for conversational purposes.
At the time
​there was
 a long thread about possible changes to the QL expansion bus, which you
can find here: http://qlforum.co.uk/viewtopic.php?f=2&t=729

QL2 was to be a replacement QL mainboard. It was based around a full 68020
@ 33.33MHz. It was going to be laid out on a standard PCI card template,
giving a connector of 120 pins (22+98) but in a manner not signal
compatible with PCI. I dubbed it QLI. The connectors are solid, cheap,

The QL2-BASE backplane was a simple "part-ATX" board with four passively
connected PCI sockets, ATX powered. The board could be fitted behind the
expansion port area of any miniATX, microATX case that could take four
full-height cards. A PCI connector has 120 pins (22+98). The base had
jumper connectors for sound+/-, ATX momentary switch, drive LED, power LED,
reset button

The pin-out of the bus brought out all needed control lines, D0:31 and
A0:31. It could support a 4GB address range and work with *any* 68k CPU
from 68008 to 68060. There were ground pins to both sides of the PCB every
2cm, and access to 5V @ 2A and 12V @ 1A per slot. The board was 4-layer,
well grounded and very clean, signal-wise. It could sustain everything up
to theoretical ~500MHz operation.

QL-BASE could have been expanded later to SEVEN connectors while retaining
signal integrity.

The QL2-IO card implemented the main functions of the original QL,
including video, ROM, serial, joystick, keyboard, sound but not
microdrives. Sound +/-, /RST drive activity LED signals are also carried on
the bus. It is required by the QL chipset that all components using DA0:7
be on a single card for obvious reasons.

The QL2-CPU card implemented the CPU and optional expansion RAM.

The QL2-EXP card would have implemented ethernet and USB - the part I am
trying to bring to fruition this year and which le
​d me to
 dig this up.

Any card could be upgraded independently without having to replace

The backplane would have been around $40. QL2-IO around $60, QL2-CPU around
$60 (1MB) $80 (8MB) $100 (16MB). Others could have produced up to 4GB
versions. It could have supported an Aurora re-implemented on a new PCB. It
left wide open the option of creating new independent video hardware and
ignoring the 8301 video function. Removing video handling from the 8301 so
simplifies it that it could have been replaced by an aftermarket CPLD with
'relatively little work.'

The AMP 5145154-1 pin out was:

 1   GND  GND
 2   12V  12V
 3   D30  D31
 4   D28  D29
 5   D26  D27
 6   D24  D25
 7   D22  D23
 8   GND  NC
 9   D20  D21
10   D18  D19
11   D16  D17
     ===  ===
12   D14  D15
13   D12  D13
14   GND  NC
15   D10  D11
16    D8  D9
17    D6  D7
18    D4  D5
19    D2  D3
20    D0  D1
21   GND  NC
22   SP0  SP1
23   SP2  SP3
24   FC0  FC1
25   FC2  /RST
26   GND  NC
27   ASL  RSVD
30  SND-  SND+
31   GND  NC
35 /IPL0  /IPL1
36  SIZ0  SIZ1
37   GND  GND
38    +5  +5
39    +5  +5
40   +12  +12
41   GND  GND
42    A0  A1
43    A2  A3
44    A4  A5
45    A6  A7
46    A8  A9
47   A10  A11
48   GND  NC
49   A12  A13
50   A14  A15
51   A16  A17
52   A18  A19
53   A20  A21
54   GND  NC
55   A22  A23
56   A24  A25
57   A26  A27
58   A28  A29
59   A30  A31
60   GND  GND

As you can see, there were 15 ground points so this interface would have
had excellent grounding.

(I am debating having the drive activity and sound connectors not be part
of the bus.)

Four +5V pins and two +12V pins would have allowed 5V @ 2A and 12V @ 1A.
Designers could have also used the VGA power system to provide extra power
to power hungry cards. The only card I could imagine needing it was a very
large RAM card. Power had large decoupling caps at each slot.

I left seven pins "NC" which were reserved and must be left not connected
in all designs. I also had four pins labeled "RSVD" which were allowed to
be connected and used for any private purpose. SPI or I2C comes to mind.
With hindsight I would have made better provision for this.

I thought it highly unlikely anyone would use over 256MB address lines over
A27, so A28:A31 would also likely have been reserved in the final spec.

I considered the option of multiplexing the data and address buses, but
decided against it for reasons of development simplicity, scalability and

I based it heavily on Nasta and Peter's discussion about the ideal QL bus
​ in the above linked thread​

OH! And I planned to include the QL-net hardware. I forgot about that!

Dave Park
QL-Users Mailing List

Reply via email to