Norman Dunbar via Ql-Users wrote:
> I've read your article. It looks interesting. I'm not clued up on
> FPGAs - although I know what the initials stand for - so, I would be
> interested in knowing a bit more about how you did the converter. If
> you have time and inclination of course.

Well, it's a bit like programming, the difference is just that
basically all lines execute at the same time! If you want something to
execute sequentially you have to implement a state machine.

That's the gist of it. If you have a base clock and base everything
off of that things are pretty clean and work nicely. But if you have
different clocks things get weird very quickly. For example I tried
implementing an Aurora card for the MiSTer FPGA board, but I couldn't
get the pixel clock to change reliably, it only worked like 50% of the

For QL-VGA I use a base clock of 130Mhz, which divides nicely into the
10Mhz QL pixel clock and the 65Mhz VGA pixel clock, so nice and clean.

Debugging is either done by simulating your code on the PC or by
actually compiling a complete logic analyzer INTO your design so it
runs on the same chip next to your own logic :-o You can then read out
your signal data using the JTAG interface. That is pretty cool.

For a pretty simple example the QL-SD code is open source if you want to
see how this looks like:
This is so small it compiles to a CPLD chip, which is basically a GAL
on drugs. But the way to code is exactly the same.

Cheers, Marcel

QL-Users Mailing List

Reply via email to