Bojan Kotur wrote:
>
> I'm looking for the 'pin assignment' scheme for QL's expansion slot.
According to the classic QL manual the connector is a 64-way male
DIN-41612 indirect edge connector and has the following connections:
----------
| *|
GND | a 1 b | GND
D3 | a 2 b | D2
D4 | a 3 b | D1
D5 | a 4 b | D0
D6 | a 5 b | ASL
D7 | a 6 b | DSL
A19 | a 7 b | RDWL
A18 | a 8 b | DTACKL
A17 | a 9 b | BGL
A16 | a 10 b | BRL
CLKCPU | a 11 b | A15
RED | a 12 b | RESETCPUL
A14 | a 13 b | CSYNCL
A13 | a 14 b | E
A12 | a 15 b | VSYNCH
A11 | a 16 b | VPAL
A10 | a 17 b | GREEN
A9 | a 18 b | BLUE
A8 | a 19 b | FC2
A7 | a 20 b | FC1
A6 | a 21 b | FC0
A5 | a 22 b | A0
A4 | a 23 b | ROMOEH
A3 | a 24 b | A1
DBGL | a 25 b | A2
SP2 | a 26 b | SP3
DSMCL | a 27 b | IPL0L
SP1 | a 28 b | BERRL
SP0 | a 29 b | IPL1L
VP12 | a 30 b | EXTINTL
VM12 | a 31 b | VIN
VIN | a 32 b | VIN
| *|
----------
A suffix 'L' on a signal name indicates that the signal is active LOW
A suffix 'H' on a signal name indicates that the signal is active HIGH
-------------------------------------------
QL Peripheral Output Signals:
SIGNAL FUNCTION
------ --------
A0..A19 68008 address lines
RDWL Read / Write
ASL Address Strobe
DSL Data Strobe
BGL Bus Grant
DSMCL Data Strobe - Master Chip
CLKCPU CPU Clock
E 6800[8?] peripheral's clock
RED video Red
BLUE video Blue
GREEN video Green
CSYNCL Composite Sync
VSYNCH Vertical Sync
ROMOEH ROM Output Enable
FC0..FC2 Processor Status
RESETCPUL Reset CPU
-------------------------------------------
QL Peripheral Input Signals:
SIGNAL FUNCTION
------ --------
DTACKL Data Acknowledge
BRL Bus Request
VPAL Valid Peripheral Address
IPL0L Interrupt Priority Level 5
IPL1L Interrupt Priority Level 2
BERRL Bus Error
EXTINTL External Interrupt
DBGL Data Bus Grab
-------------------------------------------
QL Peripheral Bi-directional Signals:
SIGNAL FUNCTION
------ --------
D0..D7 Data Lines
-------------------------------------------
Miscellaneous
SIGNAL FUNCTION
------ --------
SP0..SP3 Select Peripheral 0 to 3
VIN +9V DC (nominal) - 500ma maximum
VM12 -12V
VP12 +12V
GND Ground
-------------------------------------------
It is not intended that the following description of the QL peripheral
expansion mechanism be sufficient to implement an actual expansion
device, but rather be read to gain a basic understanding of the
expansion mechanism.
Single or multiple peripherals may be added to the QL up to a maximum of
16 devices [was the bug that recognised only the first one found
fixed?].
...
The position of each peripheral device in the overall memory map of the
QL is determined by the select peripheral lines SP0..SP3. These select
lines generate a signal correcponding to the slot position in the QL
expansion module, thus for a device to be selected the address input
from address lines A14..A17 must be the same as the signals from
SP0..SP3 respectively.
-------------------------------------------
I can't give any further info regarding actual connection as h/ware is
not my speciality - especially the IDE as I have not knowledge of the
IDE pins.
Cm
