On 9/20/01 at 10:27 PM Peter Graf wrote:
>> Yes, the original idea behing the GoldFire was to use the
>> QXL version of SMSQ as the basis for it, as that is the
>> closest related hardware.
>
> I don't think so. The Q40 is *much* nearer to your earlier announcement
> than the QXL. Think about memory map, interrupt structure, screen memory,
> Qubide, IO chips and so on.
You are right, i should have been more precise, the QXL WAS the closest
hardware - the idea for a GoldFire was concieved long before it was
announced. It stemmed from a discussion with Stuart Honeyball about a
PCMCIA version of the QXL, and the possibility for me to do some design
work on it. However, it was soon scrapped as the announced MCF5102
continually failed to become available on the market (where have we heared
that before?). When it finally materialized (somehwere around the time the
Aurora became available) I already had plans to do a SGC successor because
it was clear Miracle was pulling out of the QL market.
>> The 040 would have to run at it's highest clock available (or close
>> enough) to compete with a (at the time) cheaper 5102
>
>The 68040 doesn't just compete, it clearly outperforms the 5102. It's a
>pity that you have cancelled the GoldFire. I would have enjoyed to see the
>Q40 win the benchmarks ;-)
Yes, though the difference would not be that spectacular. I usually
consider 6dB :-) (2x) difference as signifficant...
>>The idea is really to cover the costs of manufacture, and of course,
>>the necessary firmware, that's all.
>
>If you cover the costs, you'll "earn" a lot more than I did.
Currently I am WAY below due to the Auroras that were never sold...
>> Also, the GF has not been canceled
>
> Point of view. I remember well that you described the Coldfire
> 5102 CPU as the very heart of the GoldFire and it's multiplexed
> bus as the most essential feature that turned the project from
> fantasy into "must be done". You also ephasized the importance
> of the smaller CPU size compared to PGA chips.
Actually, the multiplexed bus gave me the idea behind the implementation of
a 32-bit bus protocol on the QL's expansion bus. Later on the multiplexed
bus reduced the number of lines needed to communicate with the logic chip,
and reduced the number of traces on the board considerably. Yes, the
ColdFire's small footprint was very important, and in fact made the
GoldFire physically possible when it was originally specced out using
72-pin SIMM RAM.
This has since been changed to SODIMM SDRAM, freeing a LOT of space. At the
time it sounded like a good idea, right now, doing anything else would be
foolish as the sprice of SDRAM is very low - it is almost a given that the
GF (or whatever it's name is going to be) will come with 128M of SDRAM as
standard, it's cheap, and if I only have to design for one configuration,
it simplifies the logic some.
Once SDRAM was in place, it even became possible to physically put BOTH the
PGA and the PQFP package, the first for a 68040V and the second for the
5102. It was a possibility which was soon discarded when the 68040V turned
out to cost about 200$ a piece in huge quantity, plus it turned out that it
would be extremely difficult to do a dual footprint PCB on 4 layers, and
retain signal integrity. That's how I came up with the SIMBUS concept, a
rehash of a very old idea I had. The extra space previously used by the
planned PGA package was used up by two buffer chips that convert the 5102
bus into the very similar SIMBUS.
Using a 68EC060, as I said in the original mail, presents a few challenges.
Space is again one of them which is why the SIMBUS concept had to be
abandoned in favor of a direct CPU to SDRAM conenction. Address lines still
have to be multiplexed externally by a LVCMOS chip, and it is going to be a
challenge fitting one onto the board, as space is again at a premium. A
little help is coming in the form of abandoning a dual footprint for the
sound chip (used to be AD1815 or 1816, now it's only 1816).
The deletion of the SIMBUS means that a lot of the potential bandwidth of
the SDRAM is wasted - the process of setting up a SDRAM access takes about
as much as the access itself. The construction of the SDRAM alowes another
access to proceed while the next is being set up. However, since the CPU
only does one access at a time, effectively doing setup-access-repeat, the
ability to use this overlap to one's advantage is lost. The SIMBUS idea
alowed two CPUs to overlap their access and thus use the SDRAM to full
advantage. SIMBUS would add a 10% memory access speed penalty for one 5102,
but two would still have a 10% penalty and be able to access the same SDRAM
- even if the wanted to do it at the same time.
Now I am back to the shared bus system using arbitration, which means that
one CPU gets 100% of all the bandwidth it can use (no overlapping), two
CPUs then share that 100% getting 50% each. On the positive side, the logic
is simpler, amongst other reasons, because the 68060 arbitration is better
than either 5102 or 68040, and there is no speed penalty when one CPU is
used, which is going to be the prevalent configuration anyway.
>Now this announced GoldFire CPU and its long promoted "must be" features
>are gone! Why not admit that it is cancelled? Even if you re-use the
>peripherals, your new announcement is something different than the
>GoldFire, and has moved somewhat into the direction of the Q60. (Not a bad
>direction ;-))
I believe the above explains it somewhat, it's more of a step back to older
concepts that were rejected when the decision was made to use the ColdFire
CPU. Now that it's out of the picture, a lot of things needed to be
re-evaluated.
It's not only the peripherals that are re-used - in fact, everything but a
part of the PCB slightly larger than the size of the PGA package is reused.
The PCB was designed that way, it has distinct areas that can be
re-designed as needed. By now it must be obvious why :-)
>>To tell the truth, there is nothing I'd like more than cooperating in a
>>design of the 'ultimate QL'...
>
>On one hand it is nice to hear that you still have dreams. As long as
there
>are such dreams, the spirit of the QL is not dead.
>On the other hand, I never had plans or hopes to build the 'ultimate QL'.
>Because the 'ultimate QL' is a machine that will never be finished. (Which
>does not mean that unfinished machines are the ultimate QL's.)
Yes, I understand that reasoning, but when I said 'the ultimate QL' it's
really a paperware exercise, it's the carefull stripping and re-instating
the features on the way to the actual product that makes it a 'real QL'. I
do understand the need to stop fiddling with a design and finally MAKE the
blasted thing - but if you are in a situation where you can't actualy make
it (for whatever reason) - such as the situation I have - exercising the
paper in order to prepare the best design when it can eventually be made
into reality, is the only thing that remains.
Regards,
Nasta
