On 8/9/2003 at 3:25 AM Tony Firshman wrote: >I can't see any mention of 'pnp' in the datasheet. >Ah there is a jumper - 'jp1' marked 'default' to p39 EECONFIG - load >from EEPROM.
Note pins 50..58 (CA0..7), 40..48 (CB0..7), 22..31 (CC0..7) and 39 (EECONFIG), in the table on page 6. The first three sets of 8 are actually the external RAM/ROM data and address lines. A pull-up to any of these pins sets the corresponding bit of the registers inside the AT/Lantic to 1, pins left unconnected remain at 0. EECONFIG needs to be puled high in order for the AT/Lantic to use the parameters from the EEPROM rather than the said configuration pins, there is a small serial EEPROM on the board for this purpose. I would bet the jumper disables it by pulling EECONFIG low. The EEPROM also stores other data, such as the 48 bit 'unique' MAC address, which is the address of the actual ethernet node the chip is supposed to implement. Fortunately, this address can be loaded/changed later on by a driver, so the EEPROM is not really required as long as the configuration pins are set properly. Now go to page 14 and reads under '4.4 Jumpered and jumperless operation support', speciffically 'Fully jumpered configuration'. Page 25 describes in detail the functions of the bits in configuration registers A, B, C. I assume that the NE2000 compatible / AT/Lantic board needs to be set to IO operation, i.e. NOT memory mapped. This is the configuration I used for the QL design. Special attention is needed to set the interrupt mode properly. IIRC, most AT/Lantic boards I've seen use the 'coded' option, normally a GAL 16V8 or PAL 16L8 is used as the decoder, see if you can locate it on the board.
