On Sun, Jan 10, 2021 at 6:06 AM Marek Marczykowski-Górecki <
[email protected]> wrote:
>
> (...)
>
> > Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit-
> > Address: 00000000 Data: 0000
> > Masking: 00000000 Pending: 00000000
>
> This looks interesting, specifically "Count=1/32". I haven't seen many
> other devices with MSI (but not MSI-X) that has more than one vector.
>
Thanks, yes it looks like you nailed the issue. The driver is dividing
up the 32 vectors to MHI, CE, WAKE, and DP so it looks like I'll have to
attempt to fix qemu as I can't simply make the driver use one vector.
>
> (...)
>
>
> So, I've looked into qemu sources and indeed, I've found this comment[1]:
>
> /* Currently no support for multi-vector */
> if (*val & PCI_MSI_FLAGS_QSIZE) {
> XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n",
> *val);
> }
>
> Later in the code you can find also relevant register definition:
>
> /* Message Control reg */
> {
> .offset = PCI_MSI_FLAGS,
> .size = 2,
> .init_val = 0x0000,
> .res_mask = 0xFE00,
> .ro_mask = 0x018E,
> .emu_mask = 0x017E,
> .init = xen_pt_msgctrl_reg_init,
> .u.w.read = xen_pt_word_reg_read,
> .u.w.write = xen_pt_msgctrl_reg_write,
> },
>
> multi-vector is covered by bits 4-6 (mask 0x70)[2] and you can see above
> that it's emulated (emu_mask) which means qemu provides own values
> instead of passing them from the hardware and the values for those 3 bits
> are 0 (init_val).
>
> I'm not sure how hard would be implementing multi-vector support here,
> but it's clearly not there.
>
> [1]
> https://github.com/qemu/qemu/blob/master/hw/xen/xen_pt_config_init.c#L1104
> [2] https://wiki.osdev.org/PCI#Enabling_MSI
>
> (...)
>
Thanks Marek. Yes the Mismatch errors were from the same qemu code.
When I have some down time from work I'll be studying the qemu code and
figure out how to add multi vector msi support. The comment above in the
qemu code about no support for multi-vector was from 9 years ago, so I
guess it is only a high priority for me :)
-Rama
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