unruh wrote:
On 2012-01-24, DaveB <[email protected]> wrote:
In article <VUBSq.3384$%[email protected]>, [email protected] says...
Usually, that sort of hardware has a way to turn off the interrupt.
It's something like you write a bit in a register to "ACK" that
interrupt. When the external signal turns off, it clears that bit.
The info should be in the fine print if you can get a good data sheet.
I have looked carefully, and can onlyfind a bit for turning off
interrupts (which of course does not turn on again). That would be fine
if it were edge triggered, but not for level triggered.
When you program that I/O bit to "turn off" interupts on that port, it
probably clears a latch too, so that it is ready for the next change in
input level to trigger another IRQ.
See if you can find some original IBM PC schematics and bios listings on
t'interweb somewhere. We all learnt a lot back in the day from them.
The problem is that these parallel cards are different from the original
parallel cards. There use level triggered interrupts so that they can
share interrupts with other devices. The PC parallel used edge triggered
interrupts which also were unsharable.
A sharable interrupt should allow you to switch off the interrupt until
the clear edge occurs, at which point the interrupt should switch on
again.
Just about all the plugin cards and adapters since then, were designed
to behave in much the same way, if not using the same circuitry, just
integrated all into one small bit of plastic.
Nope. they are not. They use totally different interrupt numbers,
Not really significant, is it?
and logic.
The basic register setup is the same. ( braindead but legacy compatible)
I've had my fair share of "intercourse" with those, though not for pps
stuff but for talking fast to external hardware via ECP/EPP.
You have extra registers for enhanced modes: ECP EPP
and the added DMA support and any ancillary function added.
usually 400hex higher than the legacy address.
With a PCI card you get an additional PCI to ISA bridge and
some adaptive logic to interface ints to the pci logic.
forex this chip :ST78C34:
http://www.exar.com/Common/Content/Document.ashx?id=163&LanguageId=1033
or similar from TI:
http://www.ti.com/lit/ds/symlink/tl16pir552.pdf
uwe
_______________________________________________
questions mailing list
[email protected]
http://lists.ntp.org/listinfo/questions
