On Friday, February 23, 2018 at 11:08:23 AM UTC-5, David K. Storrs wrote:
> On Thu, Feb 22, 2018 at 11:14 AM, Alexander McLin <alex....@gmail.com
>> As one of those who have been following RISC-V progress for several years
>> and also interested in seeing Racket being ported to that architecture I
>> want to drop a note to let you know you have my support!
> As someone who doesn't know a lot about hardware, I'm curious: what
> effect would runningthe new architecture have? Would it enable new
> functionality, provide performance boosts...?
In the near-future, none.
RISC-V is designed to be an open-source ISA free of any royalties or
licensing concerns whatsoever. The idea is to provide a flexible family of
ISAs which can be combined as needed for one's purposes and any company or
foundry can manufacture RISC-V CPUs without restrictions. RSIC-V's long
term goal is to become a universal ISA anyone can use in contrast to X86 or
ARM which come with hefty licensing fees and restrictions on who can
manufacture chips which makes it difficult for anyone else to innovate in
As for enabling new functionality, one major goal for RISC-V is to allow
the ISA to be extended in well-defined ways which preserve backward
compatibility but allow innovative features to be enabled for specific
applications. It remains to see how successful that would be. My
expectation is better support for hardware-based security features and
audit of hardware designs by independent parties which is significant given
how the Meltdown and Spectre vulnerabilities have highlighted the opaque
nature of the closed-source X86 hardware.
Once anyone who's interested can at relatively low costs explore the design
space of possible RISC-V hardware, who knows what performance benefits may
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