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ICDS – Front End

* Front end ASIC Design/ RTL Design & verification.

* Proficiency in VerilogVera/ Specman,

* Exposure to C/ C++ is an advantage.

* Must have developed test benches / verification environment for a few modules/ full  chip on several projects.

 

Exp - 3 to 6 yrs

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DFT Engineers

* Digital Design experience.

* Internal Scan, Memory BIST, Boundary scan, JTAG, NAND tree.

* Test vector generation, ATPG, post silicon verification.

* Scripting - Perl, Tcl/ Tk.

* Knowledge of synthesis, timing closure - STA and P&R flow.

 

Exp - 2 to 7 yrs

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BACK-END/ PHYSICAL DESIGN Engineers (Bangalore)

* ASIC physical design includes full chip P&R flow, clock tree synthesis, SI, physical verification-DRC/LVS.

* IO cell development, automation using Perl. * Exposure to Cadence, Magma and Synopsys suite of tools.

* Must have worked on one full-chip tapeout with timing closure using Prime Time.

 

Exp - 2 to 7 yrs

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Datacom:

Datacom Development :(Routing Protocols)

Yrs of Exp - 2 – 8 yrs

ü       Strong C Programming Skills

ü       Exposure to DSLAM/ IPv4/ IPv6/ ATM / IPSEC/OSPF/ BGP/ ICMP/ PIM/ IGMP/ STP/ RSTP/ LACP/ MPLS/ VPLS/ RTP/RTCP/RIP/Network Processors

VOIP/SIP Development

ü       Very Good C Programming Skills

ü       IPv4 / IPv6 (Software IP Forwarding), SIP-PSTN gateway / VOIP/ SIP-Server/ SIP UA/Call Processing /FSM / Dial Plan / Routing Engine / Tables/Digit Manipulation)/T1/E1 CAS Signaling /ISDN PRI/BRI/Q.SIG (trillium stack preferred)

Datacom Testing

Yrs of Exp - 5 – 9 yrs (Tech Prime Role – Individual Contributor.)

ü       Hands on Test Automation Experience in Datacom routing protocols

ü       Working Knowledge of IPSec/ VPN/ Firewall/ BGP/ MPLS/ OSPF/ RIP/ TCP/IP/ UDP/ DSLAM/ IPv4/ IPv6/ ATM/ ICMP/ PIM/ IGMP/ STP/ RSTP/ LACP// VPLS/ SDH/ SONET/ DWDM/ DSL/RTP/RTCP/RIP

Good scripting experience in Tcl / Tk or Perl

 

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DSP, Layer1

 

Yrs of Exp: 3 – 10 yrs

Preferred - Engineering Graduates with Digital Communication Background(ECE/EEE)

ü       Experience in DSP, Layer 1/2/3 Development, Physical Layer Development.

ü       Experience in DSP/BIOS/Firmware Development/ Debugging/ Base band Processor/Physical Layer/Layer 1 /Layer 2/ RLC / MAC Layer

ü       Experience is VDSP/ADSP/Filter design and implementation.

ü       Good exposure and work experience in C Programming and the Implementation.

 

 

Date of Birth (Mandatory) -

Current Salary –

Expected Salary –

Joining Period –

Ready to relocate to Bangalore (Y/N)

Regards
Rajashree
career connexions
26712127 , 26710002

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CAREER CONNEXIONS, BANGALORE, INDIA


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