I found the schematic yesterday and found that PIN 14 is XMIT PL INHIBIT and PIN 5 is PL INDICATOR. Now the TX PL is active only on valid PL on the receive side !!
Thank's to all who helped me. I appreciated. Eric VE2TSO --- In [email protected], "kk2ed" <kk...@...> wrote: > > I believe Pin 14 on the PL board is the encode disable pin. Simply grounding > this pin disables the encoder. You can also find a COS signal at pin 5 of > the squelch gate slot. It is active high. > > Using two NPN transistors, and a few 10k resistors, you can have the COS > drive the first transistor, which will pull it's collector low during rx > activity, and turn off the second NPN. When there is no COS activity, the > second NPN will be biased on, and it's collector will pull the pin 14 encode > disable pin low. > > Eric > K2WD > > > --- In [email protected], "Eric" <ve2tso@> wrote: > > > > Hello, > > > > Is there a way to configure the TRN5073A PL board to TX PL only during COR > > ? Actually, PL is always ON, even during the dropout delay. > > > > I don't have the TRN5073A schematic, only for the TRN5075A. > > > > Q201, Q202 and some resistors/diode are missing on my board. Guess I need > > them to control the PL ?? > > > > Sincerely, > > Eric VE2TSO > > >
