On 28/07/15 08:15, Bob Summerwill wrote:
Have you seen ...
https://github.com/testaco/whitebox
http://radio.testa.co/
Perhaps there might be a path here around all the baseband woes?
FPGAs generally don't have open source toolchains. Yosys supports the
icestick, which I own (an exception), but AFAIK cannot be programmed in
MyHDL, only verilog. Also, all digital phase lock loops apparently have
a higher phase noise.
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