*Greetings from Robert,*

*Location: Redmond, WA*

*Duration: 1 year +*

*Requirement - 1 (2 positions)*Position: PCB Layout Designer

Job Description: The Microsoft Surface Team is looking for “local”
experienced Cadence Allegro PCB Designers. Key Duties and Responsibilities
will include: ·         Schematic capture, symbol creation, placement,
connection, netlist and BOM generation using Orcad Capture CIS or Cadence
Concept Design Entry HDL. ·         Complete Placement and Layout of HDI
Circuit Board Designs and FPC’s with Cadence Allegro PCB Editor. ·
Generate all Fab and Assembly Packages (ODB++ or IPC-2581). ·
Interface with EE and ME staff for design development and solving board
level related issues. ·         Work in a collaborative environment with
multiple designers on a single design. Required Skills ·         Proficient
in Cadence Allegro PCB Editor and Constraint Management ·
Experience with Analog design layout techniques ·         Experience with
RF design layout techniques (plus) ·         Experience with Switch Mode
Power Supply layout techniques ·         Experience with Impedance Control
and Transmission Line Theory ·         Experience with Downstream BluePrint
and CAM350 (plus) ·         Excellent organization and communications
skills ·         Ability to work well with a diverse group of dedicated

*Required Experience* ·         5 to 10 Years Industry Experience
performing PCB Design using Cadence Allegro PCB Editor   v   The Ideal
candidate will be capable to taking a hand drawn schematic or concept and
deliver a fully assembled PCBA and have recent layout experience in PC,
Tablet and motherboard designs.

*Requirement - 2 (1 positions)**​**Position: PCB Library creation engineer*

Job Description:.ECAD Librarian/ Application Engineer     To be part of a
team of electrical engineers who are responsible for specifying, designing
(creating/maintaining the component symbol and footprint libraries,
maintaining 2D and 3D library, schematic capture (Cadence Concept and Orcad
CIS), component placement, setting up design constraints, routing and post
process of complex, high speed, multilayer printed circuit boards (Cadence
Allegro), analog/digital circuit design, BOM, cost analysis), implementing

verifying motherboard and component technology vehicles with considerations
for design for manufacturability, test, assembly, EMC and EMI. Application
configuration skills and experience is highly   preferred (Cadence ADW,
ECAD MCAD data exchange setup, ECAD connectors with PDM and PLM solutions,
etc)This requires a strong team player who is has strong communication
skills, be a change agent,  has the ability to learn quickly, analyze and
implement new interfaces and subsystems, break down complex issues and

across cross functional teams to resolve issues in a timely manner and is
able to clearly express ideas in verbal and written forms. Must be able to

work, and work to a plan adapting as necessary in a rapidly evolving
environment. This includes development of requirements by working with team
members evaluating different solution options for functionality, cost and
risk, developing the solution, implementing it, verifying it and supporting
it in use.


۰BS in EE required

۰5-10 years of relevant library management experience * OrCAD/ Cadence
Allegro tools experiences - minimum 5 years* Expertise in DFM / DFX * Solid
understanding of materials in electronic and electomechanical components.

*With Regards,*

*Robert | Business Development Manager | Platinum Infosys Inc*

*Email: **rob...@platinuminfosys.com <rob...@platinuminfosys.com>** |
Phone: *214-550-0248* | Fax: *214–260–1160

*Visit us @ **www.platinuminfosys.com <http://www.platinuminfosys.com/>*

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