*Hi Associate,Please go through the Job Description and let me know your
Interest ." Reply me at vi...@itscient.com
<vi...@itscient.com> "Position: System Verilog/ Verification Engineers
VLSILocation: San Jose,CADuration: 6+MonthsJOB DESCRIPTION :- - System
Verilog - SV - VLSI HVL Verification - hands-on SV/UVM experience As a
Lead, you are responsible for managing a small team of analysts,
developers, testers or engineers and drive delivery of a small module
within a project (Delivery/Maintenence/Testing) You may serve as entry
level specialist with expertise in particular technology/industry domain/a
process / application / product. You are responsible for
functional/technical track of a project.Minimum work experience: 5 - 8
*Thanks and regards,*
* Vicky Menon *
*Sr.Technical Recruiter || IT-SCIENT || Phone: 510.972.5217 ||
Fax: 877.701.4872 || Email:vi...@itscient.com
<email%3avi...@itscient.com> ||Web: www.itscient.com
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