Pleasure mailing you. We have an immediate requirement with one of our
Global Implementation partner. Below is the details Job description, Please
go through the JD.
If you have any suitable consultants matching with the requirement, Please
send me the updated resume along with contact details, work authorization
status, availability, expected hourly rate.
Early response is really appreciated.
*Job Title: VLSI Digital DFT And Test Architect /consultant*
Location: Lebanon, PA
Duration: 12+ Months
Required Skill(s) Hardware Designing (L2) , ATPG - VLSI
Automatic Test Pattern Generation (L4) , Static Timing analysis (L4) , VLSI
Built In Self Test - BIST (L4) , VLSI Memory BIST and Boundary SCAN (L3) ,
VLSI Design For Testability - DFT (L3)
Essential Skill(s) VLSI Test and Product Engineering (L4)
Additional Skill(s) International Logistics (L1) , Production
Skill1 - *Hardware Designing (L2)*
Responsible for the schematic entry, circuit design, circuit
debugging,simulation, layout & verification of complex components of a chip
block. Workson problems of relatively complex scope, through general usage
of standarddesign concepts and principles and application of own judgment.
Works as afully contributing team member, under broad supervision/
guidance. Requiressolid knowledge of at least one design area. Expected to
further build upondomain knowledge and technical/ proprietary skills to
reach levels ofexpertise. May guide new members in the team to help them
scale up faster
Skill2 - *ATPG - VLSI Automatic Test Pattern Generation (L4)*
Able to do Silicon debug and diagnostics. Delay tests using PLL ,
silicondebug and diagnostics.
Skill3 - *Static Timing analysis (L4)*
Competent in basics of timing analysis. Can perform a full block level
timinganalysis. Can perform a full IP level synthesis and timing analysis.
Canperform a full chip STA with multiple clock domains. Able to setup Full
chipLevel Timing Constraint, False path, Multi-cycle path, timing
exceptions. Ableto debug & resolve Complex timing issues like SI and Xtalk.
Perform timinganalysis with physical data such as SPEF parasitic.
Knowledgeable on modeanalysis,case analysis and On Chip Variation (OCV)
timing analysis.Knowledgeable on timing optimization strategies and be able
to suggestarchitectural/micro-architecturalool based techniques for timing
Skill4 - *VLSI Built In Self Test - BIST (L4)*
Good knowledge of On-chip scan compression or bist techniques and test time
reduction.Memory BIST integration in SoC and verification, selecting the
optimal memory bist configuration for SoC.Insertion and verification, X
propogation and design issues and guidelines. Algorithm selection and BISTt
architecturedefinition and diagnostics.Handling multiple LBIST or multimode
scan compressions in SoC, AT- speed ATPG with logic bist or scan
compression, silicon debug and diagnostics. Flash testing, Memory repair
and Silicon debug.
Skill5 - *VLSI Memory BIST and Boundary SCAN (L3)*
Skill6 - *VLSI Design For Testability - DFT (L3)*
Skill1 - *VLSI Test and Product Engineering (L4)*
Skill1 - *International Logistics (L1)*
Skill2 - *Production Planning (L1)*
Should have knowledge of at processes in Production Planning /
ManufacturingShould understand in detail one of the Production Planning /
Manufacturingfunctions like Long Term Planning, Capacity Planning and
Leveling, MaterialPlanning, Production Scheduling and Leveling, Order
execution and reporting.Should have understanding of the Master data
required for the ProductionPlanning / Manufacturing processes
Thanks & Regards,
Prosercorp d.b.a Tekskills Inc
ISO 9001: 2008 Certified Company
Phone:732-640-2152 |Fax: 888-543-5125
200, MetroplexDrive, Suite414, Edison, NJ – 08817
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