*Please send the resumes to "divya_das...@aesinc.us.com
*Role:** ASIC Physical Design Engineer*
*Duration:** 6 months (extension possible)*
*Location:** Chandler, AZ or Austin, TX *
*Phone Screen+ Skype*
*Rate: Open on C2C/ W2*
*Job Description *
· Bachelor’s degree or foreign equivalent required.
· 4 to 6 years of experience in ASIC Physical Design
· At least 4 years of experience in the following skills -
Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock
tree synthesis), Static Timing Analysis, Formal Verification, Physical
Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power
Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process
· Desired Tools Experience: Synopsys ICC flow, Prime Time,
Design Compiler, Redhawk, LEC/Formality, and Caliber.
· At least 4 years of experience in Project life cycle
activities on development and maintenance projects.
· At least 4 years of experience in Physical Design and
· At least 4 years of experience in ASIC development life
· Ability to work in team in diverse/ multiple stakeholder
*Marie D Dasari630-315-9569*
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