My preference is to keep the bridges associated with the overlay and
handling the bridge addressing. I say this because when bridges included
in the FPGA region itself are added you will have to handle this in the
fpga region and i prefer that the handing of bridges remain consistent.
For example, sa a qsys system includes a bridge (in fpga logic) to a fpga
region. I would expect the fpga region to describe the bridge and its
peripherals.
Also, how would you handle the f2sdram bridge where there is no real
addressing associated to the proc? an FPGA region may require that to be
enabled. I have been playing with this on the atlas board. Here is my
overlay. What is missing in the fragment below is that newer fpga-region
support allows for the bridges associated with the fpga region to be
defined in the region itself.
/*
* This devicetree is generated by sopc2dts version
Release-08-10-16_13.17.35-2-g3374177-dirty on Mon Sep 26 13:48:44 PDT 2016
* Sopc2dts is written by Walter Goossens <waltergooss...@home.nl>
* in cooperation with the nios2 community <nios2-...@lists.rocketboards.org
>
*/
/dts-v1/ /plugin/;
/include/ "fpga_overlay.dtsi"
/ {
fragment@0 {
target-path = "/soc/base-fpga-region";
__overlay__ {
firmware-name = "ATLAS_SOCKIT_GHRD.rbf";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0xc0000000
0x20000000>,
<0x00000001 0x00000000 0xff200000
0x00200000>;
onchip_memory2_0: memory@0x000000000 {
device_type = "memory";
compatible = "ALTR,onchipmem-16.0";
reg = <0x00000000 0x00000000 0x00008000>;
clocks = <&clk_0>;
}; //end memory@0x000000000 (onchip_memory2_0)
jtag_uart: serial@0x100002000 {
compatible = "altr,juart-16.0",
"altr,juart-1.0";
reg = <0x00000001 0x00002000 0x00000008>;
interrupt-parent = <&intc>;
interrupts = <0 40 4>;
clocks = <&clk_0>;
}; //end serial@0x100002000 (jtag_uart)
a_16550_uart_1: serial@0x100009000 {
compatible = "altr,altera_16550_uart-16.0",
"altr,16550-FIFO128", "ns16550a";
reg = <0x00000001 0x00009000 0x00000200>;
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
clocks = <&clk_0>;
clock-frequency = <50000000>; /*
embeddedsw.dts.params.clock-frequency type NUMBER */
fifo-size = <128>; /*
embeddedsw.dts.params.fifo-size type NUMBER */
reg-io-width = <4>; /*
embeddedsw.dts.params.reg-io-width type NUMBER */
reg-shift = <2>; /*
embeddedsw.dts.params.reg-shift type NUMBER */
}; //end serial@0x100009000 (a_16550_uart_1)
a_16550_uart_0: serial@0x100008000 {
compatible = "altr,altera_16550_uart-16.0",
"altr,16550-FIFO128", "ns16550a";
reg = <0x00000001 0x00008000 0x00000200>;
interrupt-parent = <&intc>;
interrupts = <0 46 4>;
clocks = <&clk_0>;
clock-frequency = <50000000>; /*
embeddedsw.dts.params.clock-frequency type NUMBER */
fifo-size = <128>; /*
embeddedsw.dts.params.fifo-size type NUMBER */
reg-io-width = <4>; /*
embeddedsw.dts.params.reg-io-width type NUMBER */
reg-shift = <2>; /*
embeddedsw.dts.params.reg-shift type NUMBER */
}; //end serial@0x100008000 (a_16550_uart_0)
sysid_qsys: sysid@0x100001000 {
compatible = "altr,sysid-16.0",
"altr,sysid-1.0";
reg = <0x00000001 0x00001000 0x00000008>;
clocks = <&clk_0>;
id = <2899645442>; /*
embeddedsw.dts.params.id type NUMBER */
timestamp = <1474922793>; /*
embeddedsw.dts.params.timestamp type NUMBER */
}; //end sysid@0x100001000 (sysid_qsys)
chip_id_read_mm_0: unknown@0x100007000 {
compatible = "unknown,unknown-1.0";
reg = <0x00000001 0x00007000 0x00000008>;
clocks = <&clk_0>;
}; //end unknown@0x100007000 (chip_id_read_mm_0)
led_pio: gpio@0x100003000 {
compatible = "altr,pio-16.0",
"altr,pio-1.0";
reg = <0x00000001 0x00003000 0x00000010>;
clocks = <&clk_0>;
altr,gpio-bank-width = <8>; /*
embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
resetvalue = <0>; /*
embeddedsw.dts.params.resetvalue type NUMBER */
#gpio-cells = <2>;
gpio-controller;
}; //end gpio@0x100003000 (led_pio)
dipsw_pio: gpio@0x100004000 {
compatible = "altr,pio-16.0",
"altr,pio-1.0";
reg = <0x00000001 0x00004000 0x00000010>;
interrupt-parent = <&intc>;
interrupts = <0 41 1>;
clocks = <&clk_0>;
altr,gpio-bank-width = <4>; /*
embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
altr,interrupt-type = <3>; /*
embeddedsw.dts.params.altr,interrupt-type type NUMBER */
altr,interrupt_type = <3>; /*
embeddedsw.dts.params.altr,interrupt_type type NUMBER */
edge_type = <2>; /*
embeddedsw.dts.params.edge_type type NUMBER */
level_trigger = <0>; /*
embeddedsw.dts.params.level_trigger type NUMBER */
resetvalue = <0>; /*
embeddedsw.dts.params.resetvalue type NUMBER */
#gpio-cells = <2>;
gpio-controller;
}; //end gpio@0x100004000 (dipsw_pio)
button_pio: gpio@0x100005000 {
compatible = "altr,pio-16.0",
"altr,pio-1.0";
reg = <0x00000001 0x00005000 0x00000010>;
interrupt-parent = <&intc>;
interrupts = <0 42 1>;
clocks = <&clk_0>;
altr,gpio-bank-width = <2>; /*
embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
altr,interrupt-type = <2>; /*
embeddedsw.dts.params.altr,interrupt-type type NUMBER */
altr,interrupt_type = <2>; /*
embeddedsw.dts.params.altr,interrupt_type type NUMBER */
edge_type = <1>; /*
embeddedsw.dts.params.edge_type type NUMBER */
level_trigger = <0>; /*
embeddedsw.dts.params.level_trigger type NUMBER */
resetvalue = <0>; /*
embeddedsw.dts.params.resetvalue type NUMBER */
#gpio-cells = <2>;
gpio-controller;
}; //end gpio@0x100005000 (button_pio)
axi_bridge_for_acp_128_0: unknown@0x100100000 {
compatible = "unknown,unknown-1.0";
reg = <0x00000001 0x00100000 0x00000008>;
clocks = <&cfg_h2f_usr0_clk>;
}; //end unknown@0x100100000
(axi_bridge_for_acp_128_0)
fft_sub_sgdma_from_fft: msgdma@0x1000a0000 {
compatible = "altr,msgdma-16.0",
"altr,msgdma-1.0";
reg = <0x00000001 0x000a0000 0x00000020>,
<0x00000001 0x000b0000 0x00000010>;
reg-names = "csr", "descriptor_slave";
interrupt-parent = <&intc>;
interrupts = <0 43 4>;
clocks = <&fft_sub_clk_0>;
}; //end msgdma@0x1000a0000 (fft_sub_sgdma_from_fft)
fft_sub_sgdma_to_fft: msgdma@0x100080000 {
compatible = "altr,msgdma-16.0",
"altr,msgdma-1.0";
reg = <0x00000001 0x00080000 0x00000020>,
<0x00000001 0x00090000 0x00000010>;
reg-names = "csr", "descriptor_slave";
interrupt-parent = <&intc>;
interrupts = <0 44 4>;
clocks = <&fft_sub_clk_0>;
}; //end msgdma@0x100080000 (fft_sub_sgdma_to_fft)
fft_sub_sgdma_from_ram: msgdma@0x1000a8000 {
compatible = "altr,msgdma-16.0",
"altr,msgdma-1.0";
reg = <0x00000001 0x000a8000 0x00000020>,
<0x00000001 0x000b8000 0x00000010>;
reg-names = "csr", "descriptor_slave";
interrupt-parent = <&intc>;
interrupts = <0 45 4>;
clocks = <&fft_sub_clk_0>;
}; //end msgdma@0x1000a8000 (fft_sub_sgdma_from_ram)
fft_sub_FFT_STadapter_0: fft_stadapter@0x1000d0000 {
compatible = "altr,fft_stadapter-1.1",
"altr,fft_stadapter";
reg = <0x00000001 0x000d0000 0x00000010>;
clocks = <&fft_sub_clk_0>;
}; //end fft_stadapter@0x1000d0000
(fft_sub_FFT_STadapter_0)
fft_sub_data: memory@0x1000c0000 {
device_type = "memory";
compatible = "ALTR,onchipmem-16.0";
reg = <0x00000001 0x000c0000 0x00010000>;
clocks = <&fft_sub_clk_0>;
}; //end memory@0x1000c0000 (fft_sub_data)
}; //end __overlay__
}; //end fragment@0
}; //end /
On Mon, Sep 26, 2016 at 1:30 PM, Walter Goossens <waltergooss...@home.nl>
wrote:
> Hi Andreas,
> Hi all,
>
> We've been discussing this a bit off-list too and thanks to Andreas'
> testing I think I'm really close to generating usable devicetree overlays.
> The thing I'm still struggling to get my fingers on is where to apply
> the overlay to exactly.
> I think that everything that is connected to the h2f_lw bridge shoud be
> overlayed on the h2f_lw bridge (fpga_bridge0) and the h2f components
> should be connected to the h2f bridge (fpga_bridge1) right? I'm fairly
> sure I can easily find the bridges all fpga-components are connecte to
> and create overlays for that. Also the gic can be reference. The only
> prerequisite is that the DT in the kernel is compiled with symbols enabled.
> If I can just reference the bridges, all address translations will be
> handled from there on.
> Unfortunately those bridges aren't in the mainlined DT, and only their
> control registers are in the altera tree. This can be sort of worked
> around by declaring a fpga_region and letting them do the hard work but
> this feels a bit backwards to me. In order to load the overlay I have to
> declare and FPGA region and then disable firmware loading because I'm
> not _really_ an fpga region...
>
> What would be the correct way forward here? I can add the
> bridge-components needed to the overlay, overlaying both the h2f_lw
> bridge and it's components, or the bridge can be properly described in
> the socfpga.dtsi. The latter has my preference of course since then I
> don't have to know the addresses at which the bridges are mapped in
> processor memory when creating the overlay.
>
> What would be the best way forward?
>
> Walter
>
> On 09/26/2016 08:25 AM, andreas.horsthe...@zf.com wrote:
> > Hello everyone,
> >
> > Is there a way to auto-generate devicetrees for kernel 4.1? SOPC2DTS is
> broken for kernels newer than 3.10.
> >
> > I think a good solution would be if we could generate a DT overlay from
> the .sopcinfo file.
> >
> > Is anyone else interrested and/or working on this?
> >
> > Andreas Horsthemke
> > _______________________________________________
> > Rfi mailing list
> > Rfi@lists.rocketboards.org
> > http://lists.rocketboards.org/cgi-bin/mailman/listinfo/rfi
> >
>
> _______________________________________________
> Rfi mailing list
> Rfi@lists.rocketboards.org
> http://lists.rocketboards.org/cgi-bin/mailman/listinfo/rfi
>
_______________________________________________
Rfi mailing list
Rfi@lists.rocketboards.org
http://lists.rocketboards.org/cgi-bin/mailman/listinfo/rfi
