Yes, the bridge is out of reset !! I can see the entires in /sys/class/fpga_bridge. At first I did have the problem of it not being out of reset (and then signal tap DOES not trigger). And the boot message will show they have not been reset properly.
ANY OTHER IDEAS? Thanks. ----- Original Message ----- From: "Mike Williamson" <michael.william...@criticallink.com> To: "Janet Estabridis" <jpe1...@mchsi.com> Cc: "rfi" <rfi@lists.rocketboards.org> Sent: Friday, January 12, 2018 10:21:20 AM Subject: Re: [Rfi] fpga2hps sdram is enabled but reading ZEROS Have you rebuilt the preloader and run the hps bridge enable handoff macro during the uBoot phase? This will take the bridges out of reset properly... -Mike On Fri, Jan 12 , 2018 at 1:10 PM, Janet Estabridis < jpe1...@mchsi.com > wrote: Thanks in advance. Previously I have done the same thing on a Macnica Sodia board but used the FPGA DDR memory to do the same thing -- so I HAVE VERIFIED that my firmware works as advertised. Currently - I want to use HPS DDR to reduce the DDR chips needed for our custom PCB so ... I am working on a Macnica Helio board took the Golden Design and added my IPs then - I have used Q17.1 bsp-editor and associated commands to generate the u-boot and preloader. If necessary I can provide those instructions. I am using kernel 4.1.22-ltsi-02999-g9689ce4 with some extra features enabled. At first my *.dtb file was not correctly resetting the bridge, but subsequently I changed the *.dtb (and from another post I matched it to the *.dtb of the kernel). AND I can see during boot [ 2.292525] fpga_manager fpga0: Altera SOCFPGA FPGA Manager registered [ 2.299650] altera_hps2fpga_bridge ff400000.fpgabridge: fpga bridge [lwhps2fpga] registered [ 2.308230] altera_hps2fpga_bridge ff500000.fpgabridge: fpga bridge [hps2fpga] registered [ 2.316543] altera_hps2fpga_bridge ff600000.fpgabridge: fpga bridge [fpga2hps] registered I HAVE SIGNAL TAP SET UP TO SEE THE avs and avm signals --> I have a device driver that has a kernel buffer of known data and I give the firmware that start address to read from BUT I can see all the correct bus signals but the data read from the address IS NOT THE EXPECTED DATA IT IS ZERO !!! What am I missing? Any help/ideas will be greatly appreciated !!! _______________________________________________ Rfi mailing list Rfi@lists.rocketboards.org http://lists.rocketboards.org/ cgi-bin/mailman/listinfo/rfi -- Mic hael Williamson Senior Engineer OpenPGP Public Key Voice: 315.425.4045 x230 http://www.CriticalLink.com 6712 Brooklawn Parkway, Syracuse, NY 13211
_______________________________________________ Rfi mailing list Rfi@lists.rocketboards.org http://lists.rocketboards.org/cgi-bin/mailman/listinfo/rfi
