2012/5/7 Jonas Wielicki <j.wieli...@sotecware.net>: > Hi folks, > > (heh, I hope this won't be too long, but its essentially just a short > question with a „bit“ of context) > > I'm still messing with ATA code to debug further SSD issues. Now I > stumbled across what rockbox code does before command issuing. Basically > its like this: > > (1) Select the device > (2) wait_for_rdy > (2a) wait_for_bsy (or return with error) > (2a.i) wait until STATUS_BSY is cleared (or timeout) > (2a) wait until STATUS_RDY is set (or timeout) > (3) Setup parameters and issue the command > > (see firmware/ata.c, searching for ATA_SELECT for reference, its done at > several places) > > However, ATA spec draft 5 (section 9.3, its at page 236 in the version I > have) has the following state graph for the bus idle mode (i.e. before a > command is being executed):
More versions of the standard can be found at http://hddguru.com/documentation (including recent ones) > > > Check_Status: > BSY = 0 & DRQ = 0 & wrong device selected > => Device_Select > BSY = 0 & DRQ = 0 & correct device selected > => Write_parameters > BSY = 1 or DRQ = 1 > => Check_Status > Device_Select: > Device selected > => Check_Status > Write_parameters: > ... do command setup etc. > > > So the spec makes no statement about the RDY bit in the status register, > so we could be timing out here indefinetly under circumstances where the > RDY bit has *not* been set before or am I getting something wrong here? >From this point of view this is correct. I mean state diagram for PIO commands doesn't mention DRDY bit. BUT section 5.14.5.2 of ATA/ATAPI-7 spec states that all devices not implementing PACKET command feature set (aka CDROMs) should set DRDY to 1 when device is capable of accepting commands. Moreover it states that device should preserve DRDY state in idle and standby modes. Anyway I am by no means ATA expert so more experienced devs should express their opinion here. MB
