It's really not hard to put object files in a subdirectory.
Your makefile is using an implicit rule to compile C files which looks
something like:
%.o : %.c
$(CC) -c $(CPPFLAGS) $(CFLAGS) -o $@ $<
You simply need to add a rule similar to this one except using the
subdirectory:
objs/%.o : %.c
$(CC) -c $(CPPFLAGS) $(CFLAGS) -o $@ $<
And change your list of objects from "foo.o bar.o" to
"objs/foo.o objs/bar.o".
I added unified diff-style comments to your code below to show you
what I mean.
I noticed your makefile handles C++ source too, so you'll need to do
the same thing with a rule for .cc files from the implicit rule:
%.o : %.cc
$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $<
Dennis
On Tue, 26 Mar 2002, Steve Boleware wrote:
> Hello list,
>
> After getting my curiosity spiked by an earlier post about
> makefiles, I determined that I would look into using makefiles
> to organize the project directory tree.
>
> I.E. having the makefile be nice and generic and find/build the
> list of all .o files for you and then creating said ofiles in a
> sub_dir of the src directory..
> Unfortunately, my understanding of makefiles and my ability
> to search the web for those who understand more about makefiles
> was not up to the task. I was able to find/modify a makefile that
> does the first part of what I was looking for, but not the second..
>
> I am pretty sure after reading "man make" that it _can_ be done,
> but I just don't know how.
>
> Below is the makefile i am using as it stands now, if anyone on the
> list can help me modify the makefile to put the .o files into a
> subdir and then link the exe using said ofiles in said dir, i would
> appreciate it very much.
>
> Thanks for taking the time to read this, :) and i hope to hear from
> someone who can help me.
>
> Steve, at a loss with makefiles.
> ----- begin makefile-----
> ####
> # HOW TO MAKE project
> # Step 1) "make clean"
> # Step 2) "make"
> ####
>
> ### Customising
> # Adjust the following if necessary; TARGET is the target
> # executable's filename, LIBS is a list of libraries to link in
> # (e.g. crypt), CFLAGS are the flags to pass to the compiler,
> # and CC is the compiler to use. You can override these on
> # make's command line of course, if you prefer to do it that way.
>
> TARGET := ../area/Rom24
> CC := g++
> CFLAGS := -Wall -g
> LIBS := crypt
> RM-F := rm -f
+OBJDIR := objs
> # You shouldn't need to change anything below this point.
>
> SOURCE := $(wildcard *.c) $(wildcard *.cc)
> OBJS := $(patsubst %.c,%.o,$(patsubst %.cc,%.o,$(SOURCE)))
-OBJS := $(patsubst %.c,%.o,$(patsubst %.cc,%.o,$(SOURCE)))
+OBJS := $(patsubst %.c,$(OBJDIR)/%.o,$(patsubst %.cc,$(OBJDIR)/%.o,$(SOURCE)))
> .PHONY : objs clean
>
> objs : $(OBJS)
>
>
> clean :
> @$(RM-F) *.o
- @$(RM-F) *.o
+ @$(RM-F) $(OBJDIR)/*.o
> @$(RM-F) *.d
> @$(RM-F) ../area/core
> @$(RM-F) $(TARGET)
>
>
> $(TARGET) : $(OBJS)
> $(CC) -o $(TARGET) $(OBJS) $(addprefix -l,$(LIBS))
+$(OBJDIR)/%.o : %.c
+ $(CC) -c $(CPPFLAGS) $(CFLAGS) -o $@ $<
> ----end makefile-------
>
>
>
>
