Author: tkreuzer
Date: Sat May 14 08:33:30 2011
New Revision: 51721

URL: http://svn.reactos.org/svn/reactos?rev=51721&view=rev
Log:
[NTOSKRNL]
Merge r51181 from cmake branch:
Move macro definition out of macro instantiation.
Fixes compilation with MSVC

Modified:
    trunk/reactos/ntoskrnl/ke/i386/cpu.c

Modified: trunk/reactos/ntoskrnl/ke/i386/cpu.c
URL: 
http://svn.reactos.org/svn/reactos/trunk/reactos/ntoskrnl/ke/i386/cpu.c?rev=51721&r1=51720&r2=51721&view=diff
==============================================================================
--- trunk/reactos/ntoskrnl/ke/i386/cpu.c [iso-8859-1] (original)
+++ trunk/reactos/ntoskrnl/ke/i386/cpu.c [iso-8859-1] Sat May 14 08:33:30 2011
@@ -474,10 +474,9 @@
             }
         }
     }
-    
+
+#define print_supported(kf_value) ((FeatureBits & kf_value) ? #kf_value : "")
     DPRINT1("Supported CPU features : %s %s %s %s %s %s %s %s %s %s %s %s %s 
%s %s %s %s %s %s %s %s\n",
-#define print_supported(kf_value) \
-    FeatureBits & kf_value ? #kf_value : ""
     print_supported(KF_V86_VIS),
     print_supported(KF_RDTSC),
     print_supported(KF_CR4),
@@ -739,7 +738,7 @@
                 /* Check if we support CPUID 0x80000006 */
                 CPUID(0x80000000, &Data[0], &Data[1], &Data[2], &Data[3]);
                 if (Data[0] >= 0x80000006)
-                {   
+                {
                     /* Get 2nd level cache and tlb size */
                     CPUID(0x80000006, &Data[0], &Data[1], &Data[2], &Data[3]);
                     
@@ -1352,7 +1351,7 @@
         
         /* Now load NPX state from the NPX area */
         FxSaveArea = KiGetThreadNpxArea(Thread);
-        Ke386FxStore(FxSaveArea);    
+        Ke386FxStore(FxSaveArea);
     }
     else
     {


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