Author: cgutman
Date: Fri Feb 24 23:05:22 2012
New Revision: 55844
URL: http://svn.reactos.org/svn/reactos?rev=55844&view=rev
Log:
[USBOHCI]
- Fix various initialization bugs
Modified:
trunk/reactos/drivers/usb/usbohci/hardware.cpp
Modified: trunk/reactos/drivers/usb/usbohci/hardware.cpp
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/drivers/usb/usbohci/hardware.cpp?rev=55844&r1=55843&r2=55844&view=diff
==============================================================================
--- trunk/reactos/drivers/usb/usbohci/hardware.cpp [iso-8859-1] (original)
+++ trunk/reactos/drivers/usb/usbohci/hardware.cpp [iso-8859-1] Fri Feb 24
23:05:22 2012
@@ -517,7 +517,7 @@
NTSTATUS
CUSBHardwareDevice::StartController(void)
{
- ULONG Control, NumberOfPorts, Index, Descriptor, FrameInterval, Periodic;
+ ULONG Control, Descriptor, FrameInterval, Periodic;
//
// lets write physical address of dummy control endpoint descriptor
@@ -530,70 +530,16 @@
WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_BULK_HEAD_ED_OFFSET),
m_BulkEndpointDescriptor->PhysicalAddress.LowPart);
//
- // get frame interval
- //
- FrameInterval = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_FRAME_INTERVAL_OFFSET));
- m_IntervalValue = OHCI_GET_INTERVAL_VALUE(FrameInterval);
-
- FrameInterval = ((FrameInterval & OHCI_FRAME_INTERVAL_TOGGLE) ^
OHCI_FRAME_INTERVAL_TOGGLE);
-
- DPRINT1("FrameInterval %x IntervalValue %x\n", FrameInterval,
m_IntervalValue);
- FrameInterval |= OHCI_FSMPS(m_IntervalValue) | m_IntervalValue;
- DPRINT1("FrameInterval %x\n", FrameInterval);
-
- //
- // write frame interval
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
-
- //
- // write address of HCCA
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET),
m_HCCAPhysicalAddress.LowPart);
-
- //
- // now enable the interrupts
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_INTERRUPT_ENABLE_OFFSET), OHCI_NORMAL_INTERRUPTS |
OHCI_MASTER_INTERRUPT_ENABLE);
-
- //
- // enable all queues
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET),
OHCI_ENABLE_LIST);
-
- //
- // 90 % periodic
- //
- Periodic = OHCI_PERIODIC(m_IntervalValue);
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_PERIODIC_START_OFFSET), Periodic);
- DPRINT("Periodic Start %x\n", Periodic);
-
- //
- // start the controller
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET),
OHCI_ENABLE_LIST | OHCI_CONTROL_BULK_RATIO_1_4 |
OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
-
- //
- // wait a bit
- //
- KeStallExecutionProcessor(100);
-
- //
- // is the controller started
- //
- Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_CONTROL_OFFSET));
-
- //
- // assert that the controller has been started
- //
- ASSERT((Control & OHCI_HC_FUNCTIONAL_STATE_MASK) ==
OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
- ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
- DPRINT1("Control %x\n", Control);
-
- //
// read descriptor
//
Descriptor = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_RH_DESCRIPTOR_A_OFFSET));
+
+ //
+ // get port count
+ //
+ m_NumberOfPorts = OHCI_RH_GET_PORT_COUNT(Descriptor);
+ DPRINT1("NumberOfPorts %lu\n", m_NumberOfPorts);
+ ASSERT(m_NumberOfPorts < OHCI_MAX_PORT_COUNT);
//
// no over current protection
@@ -620,66 +566,83 @@
WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_RH_DESCRIPTOR_A_OFFSET), Descriptor);
//
+ // get frame interval
+ //
+ FrameInterval = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_FRAME_INTERVAL_OFFSET));
+ m_IntervalValue = OHCI_GET_INTERVAL_VALUE(FrameInterval);
+
+ FrameInterval = ((FrameInterval & OHCI_FRAME_INTERVAL_TOGGLE) ^
OHCI_FRAME_INTERVAL_TOGGLE);
+
+ DPRINT1("FrameInterval %x IntervalValue %x\n", FrameInterval,
m_IntervalValue);
+ FrameInterval |= OHCI_FSMPS(m_IntervalValue) | m_IntervalValue;
+ DPRINT1("FrameInterval %x\n", FrameInterval);
+
+ //
+ // write frame interval
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
+
+ //
+ // HCCA alignment check
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET),
0xFFFFFFFF);
+ KeStallExecutionProcessor(10);
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET));
+ ASSERT((m_HCCAPhysicalAddress.LowPart & Control) == Control);
+
+ //
+ // write address of HCCA
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET),
m_HCCAPhysicalAddress.LowPart);
+
+ //
+ // now enable the interrupts
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_INTERRUPT_ENABLE_OFFSET), OHCI_NORMAL_INTERRUPTS |
OHCI_MASTER_INTERRUPT_ENABLE);
+
+ //
+ // enable all queues
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET),
OHCI_ENABLE_LIST);
+
+ //
+ // 90 % periodic
+ //
+ Periodic = OHCI_PERIODIC(m_IntervalValue);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_PERIODIC_START_OFFSET), Periodic);
+ DPRINT("Periodic Start %x\n", Periodic);
+
+ //
+ // start the controller
+ //
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET),
OHCI_ENABLE_LIST | OHCI_CONTROL_BULK_RATIO_1_4 |
OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
+
+ //
+ // wait a bit
+ //
+ KeStallExecutionProcessor(100);
+
+ //
+ // is the controller started
+ //
+ Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_CONTROL_OFFSET));
+
+ //
+ // assert that the controller has been started
+ //
+ ASSERT((Control & OHCI_HC_FUNCTIONAL_STATE_MASK) ==
OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
+ ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
+ DPRINT1("Control %x\n", Control);
+
+ //
// enable power on all ports
//
WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_STATUS_OFFSET),
OHCI_RH_LOCAL_POWER_STATUS_CHANGE);
//
- // wait a bit
- //
- KeStallExecutionProcessor(10);
-
- //
- // write descriptor
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_RH_DESCRIPTOR_A_OFFSET), Descriptor);
-
- //
- // retrieve number of ports
- //
- for(Index = 0; Index < 10; Index++)
- {
- //
- // wait a bit
- //
- KeStallExecutionProcessor(10);
-
- //
- // read descriptor
- //
- Descriptor = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_RH_DESCRIPTOR_A_OFFSET));
-
- //
- // get number of ports
- //
- NumberOfPorts = OHCI_RH_GET_PORT_COUNT(Descriptor);
-
- //
- // check if we have received the ports
- //
- if (NumberOfPorts)
- break;
- }
-
- //
- // sanity check
- //
- ASSERT(NumberOfPorts < OHCI_MAX_PORT_COUNT);
-
- //
- // store number of ports
- //
- m_NumberOfPorts = NumberOfPorts;
-
- //
- // print out number ports
- //
- DPRINT1("NumberOfPorts %lu\n", m_NumberOfPorts);
-
-
- //
// done
//
+ DPRINT1("OHCI controller is operational\n");
return STATUS_SUCCESS;
}
@@ -912,18 +875,10 @@
NTSTATUS
CUSBHardwareDevice::StopController(void)
{
- ULONG Control, Reset, Status;
+ ULONG Control, Reset;
ULONG Index, FrameInterval;
//
- // alignment check
- //
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET),
0xFFFFFFFF);
- Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET));
- //ASSERT((m_HCCAPhysicalAddress.QuadPart & Control) == Control);
-
-
- //
// check context
//
Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_CONTROL_OFFSET));
@@ -931,14 +886,9 @@
if ((Control & OHCI_INTERRUPT_ROUTING))
{
//
- // read command status
- //
- Status = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_COMMAND_STATUS_OFFSET));
-
- //
// change ownership
//
- WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_COMMAND_STATUS_OFFSET), Status | OHCI_OWNERSHIP_CHANGE_REQUEST);
+ WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_COMMAND_STATUS_OFFSET), OHCI_OWNERSHIP_CHANGE_REQUEST);
for(Index = 0; Index < 100; Index++)
{
//
@@ -1002,7 +952,7 @@
// check control register
//
Control = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base +
OHCI_CONTROL_OFFSET)) & OHCI_HC_FUNCTIONAL_STATE_MASK);
- if (Control & OHCI_HC_FUNCTIONAL_STATE_RESUME)
+ if (Control == OHCI_HC_FUNCTIONAL_STATE_RESUME)
{
//
// it has resumed
@@ -1086,7 +1036,7 @@
//
// reset time is 10ms
//
- for(Index = 0; Index < 10; Index++)
+ for(Index = 0; Index < 100; Index++)
{
//
// wait a bit
