*MUST BE LOCAL & COME FOR F2F !!!!!!!!!!!!* *QA Tester with CMOS (TSMC 65nm 45/40nm or smaller geometries) * *Santa Clara ,CA Duration is 3 to 6 months.*
QA Tester with intrinsic reliability experience. They are looking for someone with either test/measurement experience, test structure layout experience related to these devices, and/or experience in evaluating data/information related to these processes. Experience evaluating foundry processes would be great. Concentration mainly on submicron CMOS (TSMC 65nm 45/40nm or smaller geometries) process technologies. Intrinsic reliability issues/concerns include: HCI, NBTI, EM, etc. How many yrs of professional exp do you have? How many yrs of exp as a QA tester? How many yrs of exp with the following: CMOS process technologies TSMC 65nm TSMC 45/40nm or smaller geometries Evaluating foundry processes Intrinsic reliability HCI NBTI EM ======================== Santhosh [email protected] [email protected] 201-255-0319 Ext 274 --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Cisco Systems" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/routeroptions -~----------~----~----~----~------~----~------~--~---
