On Tue, Jan 27, 2009 at 11:23:33PM +0000, Timothy Coltman wrote: > Using 4.02 I get exactly the same error. I've had a look at the > source for the module and there looks to be an error: > > cmhg.ModHdr says "swi-chunk-base-number: 0x58cc0". Presumably this > means that any SWIs issued by the module will start from this number. > However, the code in "s.intveneer" is issuing &56ac4. If this is an > EtherRPCEm SWI, shouldn't it be a &58cc0 number?
No: EtherRPCEm_ SWIs start at &58CC0. These are mostly DCI4 functions called by the Internet stack, involved in getting the driver chain established (along with various service calls, because the modules can be started in any order). ArcEm_ SWIs begin at &56AC0. There isn't a module that implements them, the emulated hardware SWI vector intercepts them and sends them off to the native Linux/Windows/etc (networking/HostFS/etc) code. It should then return to the ARM code caller in a manner that looks like the SWI dispatched correctly. The RISC OS SWI dispatcher should never see these SWIs being called. (And thus the SWI names probably don't exist as far as RISC OS is concerned) In effect EtherRPCEm is translating calls from the Internet module (the EtherRPCEm_ SWIs are fairly incidental here - most of the work is done by direct function calls by Internet into EtherRPCEm) into ArcEm_ SWIs which call the emulator. In this case EtherRPCEm is a fairly thin translation layer - all of the interesting networking stuff happens in the emulator's native code. I don't know why RPCEmu isn't intercepting the &56AC4 SWI, but that's the problem: RISC OS is bouncing it because it hasn't been intercepted by the emulator. That would be where to look. Are you sure your emulator has networking enabled? In the code (in arm.c or ArmDynarec.c, search for ARCEM) the Linux network support would seem to be #ifdefed on RPCEMU_LINUX. Are you trying to run the EtherRPCEm module on a platform that isn't Linux? Tom's Windows networking code works differently: http://www.riscos.info/pipermail/rpcemu/2007-November/000060.html but I don't know where it fits in with the current sources. > Unfortunately I can't recompile it to try it out as the 1996-vintage > C/C++ suite I've got doesn't like some of the assembly code. See > attached for a copy of the output from objasm. > Warning: MRS/MSR invalid in 26-bit PC configurations at line 114 in macro > ToSVCEAll You can build 32 bit stuff with Acorn C v5, but I think you need some extra options. A quick Google suggests you may want '-apcs 3/32bit'. But I don't think you want to be changing the SWI called :-) Theo _______________________________________________ Rpcemu mailing list [email protected] http://www.riscos.info/cgi-bin/mailman/listinfo/rpcemu
