Hi, I'd like to alter my applications and sound modules so that they will work on the ARMv7 which means duplicating some routines to use LDRH ou LDRSH instructions instead of halfword aligned LDRs when they are supported by the machine. I was wondering how to test that code with having any machine that support these instructions when I thought of RPCEmu. The StrongARM instruction set includes them but they are not working correctly on a real RPC due to the RPC memory bus, but is this also true for RPCEmu? It also makes me think it could be interesting to create some hybrid CPU targets which basically behave like the StrongARM so that the existing versions of RISC OS and applications work on it but with the extended instructions sets from the XScale or the OMAP. It would allow developers to write code taking avantage of new CPUs without having the real hardware at hand. Next, once RISC OS 5 and more applications support these CPUs, ROOL could perhaps retrofit this support in the experimental RISC OS 5 for the RPC and RPCEmu would be able to introduce a full simulatation of these CPUs (lack of 26-bit mode, non-rotational behaviour of halfword aligned LDRs, etc). Kind Regards, André Timmermans
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