Thomas Doerfler wrote:
Chris,
Am 23.06.2013 03:46, schrieb Chris Johns:
Thomas Dörfler wrote:
Note that the pages usually only cover 4K of
memory, and the "translation lookaside buffer" (TLB) only maintains the
last 16-64 used pages,
The ARM which I am currently using and have handy seems to support 1MB,
64K and 4K ranges depending on the TLB table level used. I would be
surprised if an entry was needed for each page in use.
Classic PowerPC ist not that flexible. The 603(e) core, that is quite
often used in PPC controllers, has a fixed page table entry size of 4K,
so the number of TLB entries (the "page cache") will never cover the
whole lot of pages for a suitable memory size.
Interesting and thanks. It is a difficult API to make because of these
reasons. Hesham has some interesting challenges.
So for this derivative (and many others) it's "Use (statically
initialized) BATs or (dynamically reloaded) TLB entries".
Agreed. Is this worth adding to the API ?
Chris
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