---
.../libbsp/arm/shared/arm-a9mpcore-clock-config.c | 21 ++++++++++++++++----
1 Datei geändert, 17 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)
diff --git a/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c
b/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c
index e32657d..cb3588f 100644
--- a/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c
+++ b/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c
@@ -105,17 +105,30 @@ CPU_Counter_ticks _CPU_Counter_read(void)
return gt->cntrlower;
}
-static void a9mpcore_clock_cleanup(void)
+static void a9mpcore_clock_cleanup_isr( rtems_irq_hdl_param arg )
{
volatile a9mpcore_gt *gt = A9MPCORE_GT;
- rtems_status_code sc;
+
+ (void)arg;
gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
gt->irqst = A9MPCORE_GT_IRQST_EFLG;
+}
+
+static void a9mpcore_clock_cleanup(void)
+{
+ rtems_status_code sc;
- sc = rtems_interrupt_handler_remove(
+ /* The relevant registers / bits of the global timer are banked
+ * and chances are, on an SPM system we are executing on the wrong
+ * CPU to reset them. Thus we will have the actual cleanup done
+ * with the next clock tick.
+ * The ISR will execute on the right CPU for the cleanup. */
+ sc = rtems_interrupt_handler_install(
A9MPCORE_IRQ_GT,
- (rtems_interrupt_handler) Clock_isr,
+ "Clock",
+ RTEMS_INTERRUPT_REPLACE,
+ a9mpcore_clock_cleanup_isr,
NULL
);
if (sc != RTEMS_SUCCESSFUL) {
--
1.7.10.4
_______________________________________________
rtems-devel mailing list
rtems-devel@rtems.org
http://www.rtems.org/mailman/listinfo/rtems-devel
