---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 110 +---------------------
1 Datei geändert, 2 Zeilen hinzugefügt(+), 108 Zeilen entfernt(-)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 2c1eb8f..fd57328 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -324,10 +324,7 @@ typedef struct {
/** @brief Drain the STB */
uint32_t cache_sync;
- uint8_t reserved_734[0x740 - 0x734];
- /** @brief ARM Errata 753970 for pl310-r3p0 */
- uint32_t dummy_cache_sync_reg;
- uint8_t reserved_744[0x770 - 0x744];
+ uint8_t reserved_734[0x770 - 0x734];
/** @brief Invalidate line by PA */
uint32_t inv_pa;
@@ -454,55 +451,6 @@ typedef struct {
uint32_t power_ctrl;
} L2CC;
-/* Errata table for the LC2 310 Level 2 cache from ARM.
-* Information taken from ARMs
-* "CoreLink controllers and peripherals
-* - System controllers
-* - L2C-310 Level 2 Cache Controller
-* - Revision r3p3
-* - Software Developer Errata Notice
-* - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310),
-* r3 releases Software Developers Errata Notice"
-* The corresponding link is:
-*
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
-* Please see this document for more information on these erratas */
-static bool l2c_310_cache_errata_is_applicable_753970(
- void
-)
-{
- volatile L2CC *l2cc =
- (volatile L2CC *) BSP_ARM_L2CC_BASE;
- const cache_l2c_310_rtl_release RTL_RELEASE =
- l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
- bool is_applicable = false;
-
- switch( RTL_RELEASE ) {
- case CACHE_L2C_310_RTL_RELEASE_R3_P3:
- case CACHE_L2C_310_RTL_RELEASE_R3_P2:
- case CACHE_L2C_310_RTL_RELEASE_R3_P1:
- case CACHE_L2C_310_RTL_RELEASE_R2_P0:
- case CACHE_L2C_310_RTL_RELEASE_R1_P0:
- case CACHE_L2C_310_RTL_RELEASE_R0_P0:
- is_applicable = false;
- break;
- case CACHE_L2C_310_RTL_RELEASE_R3_P0:
- is_applicable = true;
- break;
- default:
- assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
- || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
- break;
- }
-
- return is_applicable;
-}
-
-
static bool l2c_310_cache_errata_is_applicable_727913(
void
@@ -972,31 +920,6 @@ static void l2c_310_cache_check_errata( void )
* corruption */
assert( ! l2c_310_cache_errata_is_applicable_752271() );
- /* This erratum gets handled with a workaround: 753970 The Cache Sync
- * operation prevents further bufferable writes from merging in the store.
- Search for 753970 in cache_.h for detailed information */
-
- /* Conditions
- This problem occurs when the following conditions are met:
- 1. PL310 receives a Cache Sync operation.
- Workaround
- The proposed workaround to avoid this erratum is to replace the normal
- offset of Cache Sync operation (0x730) by another offset targeting an
- unmapped PL310 register: 0x740.
- More specifically, find below a pseudo code sequence illustrating the
- workaround:
- Replace
- // PL310 Cache Sync operation
- LDR r1,=PL310_BASE
- STR r2,[r1,#0x730]
- by
- // Workaround for PL310 Cache Sync operation
- LDR r1,=PL310_BASE
- STR r2,[r1,#0x740] ; write to an unmapped register
- This write has the same effect as the Cache Sync operation: store buffer
- drained and waiting for all buffers empty.*/
- /* assert( ! l2c_310_cache_errata_is_applicable_753970() ); */
-
/* This erratum can not be worked around: 754670 A continuous write flow can
* stall a read targeting the same memory area
* But this erratum does not lead to any data corruption */
@@ -1030,23 +953,10 @@ static void l2c_310_cache_check_errata( void )
}
static inline void
-cache_l2c_310_sync( void )
-{
- volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
-
- if( l2c_310_cache_errata_is_applicable_753970() ) {
- l2cc->dummy_cache_sync_reg = 0;
- } else {
- l2cc->cache_sync = 0;
- }
-}
-
-static inline void
cache_l2c_310_flush_1_line( const void *d_addr )
{
volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
-
if( l2c_310_cache_errata_is_applicable_588369() ) {
/*
* Errata 588369 says that clean + inv may keep the
@@ -1055,13 +965,10 @@ cache_l2c_310_flush_1_line( const void *d_addr )
* line, with write-back and cache linefill disabled.
*/
l2cc->clean_pa = (uint32_t) d_addr;
- cache_l2c_310_sync();
l2cc->inv_pa = (uint32_t) d_addr;
} else {
l2cc->clean_inv_pa = (uint32_t) d_addr;
}
-
- cache_l2c_310_sync();
}
static inline void
@@ -1079,7 +986,6 @@ cache_l2c_310_flush_range( const void *addr, size_t
n_bytes )
for (; adx <= ADDR_LAST; adx += CPU_DATA_CACHE_ALIGNMENT ) {
l2cc->clean_pa = adx;
}
- cache_l2c_310_sync();
}
}
@@ -1096,13 +1002,9 @@ cache_l2c_310_flush_entire( void )
l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
- while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {
- }
+ while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};
- ;
- /* Wait for the flush to complete */
- cache_l2c_310_sync();
}
}
@@ -1113,8 +1015,6 @@ cache_l2c_310_invalidate_1_line( const void *d_addr )
l2cc->inv_pa = (uint32_t) d_addr;
-
- cache_l2c_310_sync();
}
static inline void
@@ -1134,7 +1034,6 @@ cache_l2c_310_invalidate_range( const void *addr, size_t
n_bytes )
/* Invalidate L2 cache line */
l2cc->inv_pa = adx;
}
- cache_l2c_310_sync();
}
}
@@ -1152,8 +1051,6 @@ cache_l2c_310_invalidate_entire( void )
while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
- /* Wait for the invalidate to complete */
- cache_l2c_310_sync();
}
static inline void
@@ -1172,8 +1069,6 @@ cache_l2c_310_clean_and_invalidate_entire( void )
while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
- /* Wait for the invalidate to complete */
- cache_l2c_310_sync();
}
}
@@ -1185,7 +1080,6 @@ cache_l2c_310_store( const void *d_addr )
l2cc->clean_pa = (uint32_t) d_addr;
- cache_l2c_310_sync();
}
static inline void
--
1.7.10.4
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