FYI this test does not link on many architectures. I have a patch for the sh pending. If libcpu does not build the shared cache code and install the .h, the test does not link.
On 4/10/2014 11:25 AM, Ralf Kirchner wrote: > --- > testsuites/sptests/spcache01/init.c | 81 > ++++++++++++++++++++++++++++ > testsuites/sptests/spcache01/spcache01.doc | 1 + > testsuites/sptests/spcache01/spcache01.scn | 2 + > 3 Dateien geändert, 84 Zeilen hinzugefügt(+) > > diff --git a/testsuites/sptests/spcache01/init.c > b/testsuites/sptests/spcache01/init.c > index 2c9d184..4be1040 100644 > --- a/testsuites/sptests/spcache01/init.c > +++ b/testsuites/sptests/spcache01/init.c > @@ -37,6 +37,86 @@ const char rtems_test_name[] = "SPCACHE 1"; > > CPU_STRUCTURE_ALIGNMENT static int data[1024]; > > +static void test_misalignment(void) > +{ > + if (rtems_cache_get_data_line_size() > 0) { > + rtems_interrupt_lock lock; > + rtems_interrupt_lock_context lock_context; > + volatile int *vdata = &data[0]; > + int *tdata = &data[2]; > + const uint32_t LINE_SIZE = > rtems_cache_get_data_line_size(); > + int tcount = LINE_SIZE; > + int vcount = tcount + 3 * LINE_SIZE; > + size_t tdata_size = tcount * sizeof(data[0]); > + bool write_through; > + int i; > + int end; > + > + printf("data cache flush and invalidate test with misaligned > addresses\n"); > + > + rtems_interrupt_lock_initialize(&lock, "test"); > + rtems_interrupt_lock_acquire(&lock, &lock_context); > + > + for (i = 0; i < vcount; ++i) { > + vdata[i] = i; > + } > + > + rtems_cache_flush_multiple_data_lines(tdata, tdata_size); > + > + for (i = 0; i < vcount; ++i) { > + rtems_test_assert(vdata[i] == i); > + } > + > + for (i = 0; i < vcount; ++i) { > + vdata[i] = ~i; > + } > + > + rtems_cache_invalidate_multiple_data_lines(tdata, tdata_size); > + > + end = (tdata_size + LINE_SIZE) / sizeof(data[0]); > + > + write_through = vdata[LINE_SIZE / sizeof(data[0])] == ~LINE_SIZE / > sizeof(data[0]); > + if (write_through) { > + for (i = 0; i < end; ++i) { > + rtems_test_assert(vdata[i] == ~i); > + } > + } else { > + for( i = 0; i < end; ++i) { > + rtems_test_assert(vdata[i] == i); > + } > + } > + i = end; > + end = i + LINE_SIZE + LINE_SIZE; > + for( ; i < end; ++i) { > + rtems_test_assert(vdata[i] == ~i); > + } > + > + for (i = 0; i < vcount; ++i) { > + vdata[i] = ~i; > + } > + > + rtems_cache_flush_multiple_data_lines(tdata, tdata_size); > + rtems_cache_invalidate_multiple_data_lines(tdata, tdata_size); > + > + for (i = 0; i < vcount; ++i) { > + rtems_test_assert(vdata[i] == ~i); > + } > + > + rtems_interrupt_lock_release(&lock, &lock_context); > + rtems_interrupt_lock_destroy(&lock); > + > + printf( > + "data cache operations with misaligned addresses passed the test (%s > cache detected)\n", > + write_through ? "write-through" : "copy-back" > + ); > + } else { > + printf( > + "skip data cache flush and invalidate test with misaligned addresses" > + " due to cache line size of zero\n" > + ); > + } > +} > + > static void test_data_flush_and_invalidate(void) > { > if (rtems_cache_get_data_line_size() > 0) { > @@ -376,6 +456,7 @@ static void Init(rtems_task_argument arg) > TEST_BEGIN(); > > test_data_flush_and_invalidate(); > + test_misalignment(); > test_timing(); > > TEST_END(); > diff --git a/testsuites/sptests/spcache01/spcache01.doc > b/testsuites/sptests/spcache01/spcache01.doc > index bbc8f25..1a56be8 100644 > --- a/testsuites/sptests/spcache01/spcache01.doc > +++ b/testsuites/sptests/spcache01/spcache01.doc > @@ -17,3 +17,4 @@ directives: > concepts: > > - Ensure that some cache manager functions work. > + - Ensure they also work with misaligned addesses > diff --git a/testsuites/sptests/spcache01/spcache01.scn > b/testsuites/sptests/spcache01/spcache01.scn > index 8013945..53d3e70 100644 > --- a/testsuites/sptests/spcache01/spcache01.scn > +++ b/testsuites/sptests/spcache01/spcache01.scn > @@ -2,6 +2,8 @@ > data cache flush and invalidate test > data cache operations by line passed the test > data cache operations by line passed the test (copy-back cache detected) > +data cache flush and invalidate test with misaligned addresses > +data cache operations with misaligned addresses passed the test (copy-back > cache detected) > data cache line size 32 bytes > data cache size 262144 bytes > data cache level 1 size 32768 bytes -- Joel Sherrill, Ph.D. Director of Research & Development joel.sherr...@oarcorp.com On-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available (256) 722-9985 _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel