[ The first posting did not appear so I am sending it again. ]
On 2/05/2014 1:31 am, Giovanni Macciocu wrote:
I've rolled back the file arm/xilinq-zynq/console/zynq-uart.c to the
version before the commit of 10 Dec. 2013.
There are a number of commits on that day. Do you mean ...
http://git.rtems.org/rtems/commit/?id=6e4255d9a5b32fcf4e665eb908a2091f327ab1d3
?
Now the the UART works on the correct speed (11500) with the current
head.
The uart driver was hard coded to a specific board and PL set up before
this commit. I changed the driver to allow board specific clocks via the
weak function 'zynq_uart_input_clock'. Maybe the Zed BSP needs to
provide one of these functions or the clock value default in the
console/zynq-uart.c needs to be based on a BSPOPTS based setting. The
default is (was?) working with my zc706 board. I will test today and see
if I can find a working JTAG cable.
The Zync is difficult because clocks can be configured in different ways
for the same board via the PL and this is exported by the Xilinx tools
via the ps7_init files. Typically you need to make sure the FSBL, the PL
bitfile and the BSP all line up. The weak function here lets you at the
application level above the BSP provide the correct set up.
Chris
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