From: Christian Mauderer <christian.maude...@embedded-brains.de>
---
cpukit/score/cpu/sparc/cpu.c | 4 +++
cpukit/score/cpu/sparc/rtems/score/cpu.h | 13 +++++++--
cpukit/score/cpu/sparc/rtems/score/sparc.h | 44 ++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index ee0d622..dc960bb 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -82,7 +82,11 @@ SPARC_ASSERT_OFFSET(is_executing,
SPARC_CONTEXT_CONTROL_IS_EXECUTING);
*/
const CPU_Trap_table_entry _CPU_Trap_slot_template = {
+#ifdef RTEMS_PARAVIRT
+ 0x01000000, /* nop */
+#else /* RTEMS_PARAVIRT */
0xa1480000, /* mov %psr, %l0 */
+#endif /* RTEMS_PARAVIRT */
0x29000000, /* sethi %hi(_handler), %l4 */
0x81c52000, /* jmp %l4 + %lo(_handler) */
0xa6102000 /* mov _vector, %l3 */
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h
b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 532d882..216fc59 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -975,8 +975,15 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a straight fashion are undefined.
*/
-#define _CPU_ISR_Set_level( _newlevel ) \
- sparc_enable_interrupts( _newlevel << 8)
+#ifdef RTEMS_PARAVIRT
+ #define _CPU_ISR_Set_level( _newlevel ) \
+ _SPARC_ISR_Set_level( _newlevel << 8)
+
+void _SPARC_ISR_Set_level( uint32_t pil );
+#else
+ #define _CPU_ISR_Set_level( _newlevel ) \
+ sparc_enable_interrupts( _newlevel << 8)
+#endif
/**
* @brief Obtain the current interrupt disable level.
@@ -1192,7 +1199,7 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current
__asm__( "g6" );
void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
- #if defined(__leon__)
+ #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
static inline uint32_t _CPU_SMP_Get_current_processor( void )
{
return _LEON3_Get_current_processor();
diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h
b/cpukit/score/cpu/sparc/rtems/score/sparc.h
index 4568300..b1859ea 100644
--- a/cpukit/score/cpu/sparc/rtems/score/sparc.h
+++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h
@@ -164,17 +164,37 @@ extern "C" {
*
* This macro returns the current contents of the PSR register in @a _psr.
*/
+#ifdef RTEMS_PARAVIRT
+
+#define sparc_get_psr( _psr ) \
+ (_psr) = _SPARC_Get_PSR()
+
+uint32_t _SPARC_Get_PSR( void );
+
+#else /* RTEMS_PARAVIRT */
+
#define sparc_get_psr( _psr ) \
do { \
(_psr) = 0; \
__asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
} while ( 0 )
+#endif /* RTEMS_PARAVIRT */
+
/**
* @brief Macro to set the PSR.
*
* This macro sets the PSR register to the value in @a _psr.
*/
+#ifdef RTEMS_PARAVIRT
+
+#define sparc_set_psr( _psr ) \
+ _SPARC_Set_PSR( _psr )
+
+void _SPARC_Set_PSR( uint32_t new_psr );
+
+#else /* RTEMS_PARAVIRT */
+
#define sparc_set_psr( _psr ) \
do { \
__asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
@@ -183,27 +203,51 @@ extern "C" {
nop(); \
} while ( 0 )
+#endif /* RTEMS_PARAVIRT */
+
/**
* @brief Macro to obtain the TBR.
*
* This macro returns the current contents of the TBR register in @a _tbr.
*/
+#ifdef RTEMS_PARAVIRT
+
+#define sparc_get_tbr( _tbr ) \
+ (_tbr) = _SPARC_Get_TBR()
+
+uint32_t _SPARC_Get_TBR( void );
+
+#else /* RTEMS_PARAVIRT */
+
#define sparc_get_tbr( _tbr ) \
do { \
(_tbr) = 0; /* to avoid unitialized warnings */ \
__asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
+#endif /* RTEMS_PARAVIRT */
+
/**
* @brief Macro to set the TBR.
*
* This macro sets the TBR register to the value in @a _tbr.
*/
+#ifdef RTEMS_PARAVIRT
+
+#define sparc_set_tbr( _tbr ) \
+ _SPARC_Set_TBR((_tbr))
+
+void _SPARC_Set_TBR( uint32_t new_tbr );
+
+#else /* RTEMS_PARAVIRT */
+
#define sparc_set_tbr( _tbr ) \
do { \
__asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
+#endif /* RTEMS_PARAVIRT */
+
/**
* @brief Macro to obtain the WIM.
*
--
1.8.4.5
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