The following BSPs do not have tick support so the tests fail: arm1136jfs arm1136js arm7tdmi arm920 armcortexa9 (does not run any more) avrtest h8sim h8sxsim m32csim m32rsim moxiesim simsh1 simsh2 simsh4 v850e1sim v850e2sim v850e2v3sim v850esim v850essim v850sim
This list was provided by Joel in the following post: http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html --- c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg | 5 +++++ .../lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/avr/avrtest/make/custom/avrtest-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/h8300/h8sim/make/custom/h8sim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/m32r/m32rsim/make/custom/m32rsim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/moxie/moxiesim/make/custom/moxiesim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg | 2 ++ c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg | 2 ++ c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg | 5 +++++ .../lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim-testsuite.tcfg | 5 +++++ .../lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim-testsuite.tcfg | 5 +++++ .../libbsp/v850/gdbv850sim/make/custom/v850e2v3sim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim-testsuite.tcfg | 5 +++++ .../lib/libbsp/v850/gdbv850sim/make/custom/v850essim-testsuite.tcfg | 5 +++++ c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim-testsuite.tcfg | 5 +++++ 21 files changed, 99 insertions(+) create mode 100644 c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg create mode 100644 c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg create mode 100644 c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg create mode 100644 c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg create mode 100644 c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg create mode 100644 c/src/lib/libbsp/avr/avrtest/make/custom/avrtest-testsuite.tcfg create mode 100644 c/src/lib/libbsp/h8300/h8sim/make/custom/h8sim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/m32r/m32rsim/make/custom/m32rsim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/moxie/moxiesim/make/custom/moxiesim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg create mode 100644 c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim-testsuite.tcfg create mode 100644 c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim-testsuite.tcfg diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg new file mode 100644 index 0000000..70a1a31 --- /dev/null +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB ARM Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg new file mode 100644 index 0000000..70a1a31 --- /dev/null +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB ARM Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg new file mode 100644 index 0000000..70a1a31 --- /dev/null +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB ARM Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg new file mode 100644 index 0000000..70a1a31 --- /dev/null +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB ARM Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg new file mode 100644 index 0000000..70a1a31 --- /dev/null +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB ARM Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/avr/avrtest/make/custom/avrtest-testsuite.tcfg b/c/src/lib/libbsp/avr/avrtest/make/custom/avrtest-testsuite.tcfg new file mode 100644 index 0000000..66fa238 --- /dev/null +++ b/c/src/lib/libbsp/avr/avrtest/make/custom/avrtest-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB AVR Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sim-testsuite.tcfg b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sim-testsuite.tcfg new file mode 100644 index 0000000..fc53bd6 --- /dev/null +++ b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB H8300 Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg new file mode 100644 index 0000000..fc53bd6 --- /dev/null +++ b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB H8300 Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg b/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg new file mode 100644 index 0000000..a23046b --- /dev/null +++ b/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB M32C Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/m32r/m32rsim/make/custom/m32rsim-testsuite.tcfg b/c/src/lib/libbsp/m32r/m32rsim/make/custom/m32rsim-testsuite.tcfg new file mode 100644 index 0000000..f6837cc --- /dev/null +++ b/c/src/lib/libbsp/m32r/m32rsim/make/custom/m32rsim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB M32R Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/moxie/moxiesim/make/custom/moxiesim-testsuite.tcfg b/c/src/lib/libbsp/moxie/moxiesim/make/custom/moxiesim-testsuite.tcfg new file mode 100644 index 0000000..a729a49 --- /dev/null +++ b/c/src/lib/libbsp/moxie/moxiesim/make/custom/moxiesim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB Moxie Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg index 834a9b6..1ce3ef3 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg @@ -4,5 +4,7 @@ # Format is one line per test that is _NOT_ built. # +include: testdata/require-tick-isr.tcfg + fsdosfsname01 utf8proc01 diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg index 4bdfa49..2484ddf 100644 --- a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg @@ -4,5 +4,7 @@ # Format is one line per test that is _NOT_ built. # +include: testdata/require-tick-isr.tcfg + fsdosfsname01 utf8proc01 diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg new file mode 100644 index 0000000..2374bb2 --- /dev/null +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB SH Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg new file mode 100644 index 0000000..2374bb2 --- /dev/null +++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The GDB SH Simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e1sim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2sim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850e2v3sim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850esim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850essim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim-testsuite.tcfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim-testsuite.tcfg new file mode 100644 index 0000000..4bec8f5 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# The simulator does not have a tick interrupt. +# + +include: testdata/require-tick-isr.tcfg -- 1.8.5.2 (Apple Git-48) _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel
