At 05:57 PM 23-04-99 +0000, you wrote:
>> On a SMP machine, could one CPU do that while the other is running?
>
>Sure, but I tested Tom's idea only on a UP. Note that the new release of
>RTAI, rtai-0.1, to be sent to LLP next week, has the capability of
>forcing the timer interrupt, in fact any interrupt, to any cpu. Moreover
>I'm working on local apic timers and if you want to do that trick on
>SMP, even without using the scheduling of tasks, it could be simpler to
>use the local timer on an assigned cpu just by requesting that interrupt
>to RTAI alone. If you are interested I can help you.
>
>By the way if you are going SMP the new release of RTAI has corrected
>some subtle bugs that where not impeding the tasks to run appropriately
>but were nonetheless significant. Now we can say that SMP works fine and
>with the addition of oneshot apic timers, to be released soon, it will
>become more than simply nice. However all those additions, and the code
>cleaning for UP and useless, but safe, volatiles are not hurried to. So
>if you need Tom's trick using apic timers it can be done in advance,
>even if not at lightning speed.
>
>Let me know.
>
>Ciao, Paolo.
>
It was just a idea I wanted to test with you. Most of my IO is serial - and
the trick there is to use the FIFO's in the UART's. I do have
some // IO like PAMUX from OPTO 22, but again, I'm polling its ISA AC28
board (despite ISA, it can write and read back a bank of 8 digital IO's
in about 11 microsec on my MMX233).
Regards
_______________________________________________________
Pierre Cloutier
Tel: (450)-659-9186
Fax: (450)-659-0014
POSEIDON CONTROLS INC
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