MTRR
MTRRs are MSRs that configure an internal map of how physical address
ranges are mapped to
various types of memory. The processor uses this internal memory map to
determine the cache-ability
of various physical memory locations and the optimal method of accessing
memory loca-tions.
For example, if a memory location is specified in an MTRR as write-through
memory, the
processor handles accesses to this location as follows. It reads data from
that location in lines
and caches the read data or maps all writes to that location to the bus
and updates the cache to
maintain cache coherency. In mapping the physical address space with
MTRRs, the processor
recognizes five types of memory: uncacheable (UC), write-combining (WC),
write-through
(WT), write-protected (WP), and writeback (WB).
Earlier Intel Architecture processors (such as the Intel486 and the
Pentium processor) used the
#KEN (cache enable) pin and external logic to maintain an external memory
map and signal
cacheable accesses to the processor. The MTRR mechanism simplifies
hardware designs by
eliminating the #KEN pin and the external logic required to drive it.
APIC
The Pentium Pro processor contains an Advanced Programmable Interrupt
Controller (APIC),
referred to in the following sections as the local APIC. The local APIC
performs two main func-tions
for the processor:
It processes local external interrupts that the processor receives at its
interrupt pins and
local internal interrupts that software generates.
In multiple processor systems, it communicates with an external I/O APIC
chip. The
external I/O APIC receives external interrupt events from the system and
interprocessor
interrupts from the processors on the system bus and distributes them to
the processors on
the system bus. The I/O APIC is part of Intels system chip set.
The local APIC controls the dispatching of
interrupts (to its associated processor) that it receives either locally
or from the I/O APIC. It
provides facilities for queuing, nesting and masking of interrupts. It
handles the interrupt
delivery protocol with its local processor and accesses to APIC registers,
and also manages
interprocessor interrupts and remote APIC register reads. A timer on the
local APIC allows local
generation of interrupts, and local interrupt pins permit local reception
of processor-specific
interrupts. The local APIC can be disabled (in hardware or software) and
used in conjunction
with a standard 8259A-style interrupt controller.
I'd go to
http://developer.intel.com/design/PentiumII/manuals/
for some good .pdf documents which detail this stuff.
On Thu, 27 May 1999, Phil Wilshire wrote:
> Hi,
> I am looking for some simple definitions and explainations
> of some of the Intel interior stuff we read about in the source code.
> I have a rough idea on what these terms mean but could one , or more ,
> of you
> provide some laymans details on the following questions...
>
> What is apic ???
> HOw does it work ???
> What is Mtrr ??
> What is the TLB Cache ???
>
> If anyone has any one liners that define these terms or pointers
> to usefull information I would be most grateful.
>
> Thanks
> Phil Wilshire
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